Where, oh where, had AltiVec gone - and where is it now? - Interview with Glenn Beck, Network Products Division, Freescale Aerospace and Defense/Single Board Computing Market Segment Manager

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December 16, 2011

An oft-posed question in the military embedded space the past couple of years has been: Will Freescale ever bring AltiVec back? That question was recently answered when the company announced its AMP Series featuring - reinstated AltiVec. Managing Editor Sharon Hess interviewed Glenn Beck, Market Segment Manager for the Network Products Division, Freescale Aerospace and defense/Single Board Computing Market, in the following Q&A.

Key want-to-knows surrounded AltiVec - why the disappearing act, and is it around to stay? - in addition to how Freescale plans to help mitigate the industry's power-versus-performance paradox. And there's a little about systems security, too. Edited excerpts follow.

What is the focus of the division you work for at Freescale?

BECK: I’m with the Network Products Division. We have responsibility for Power Architecture technology, where we build processors primarily for the networking and telecom marketplace as well as the general industrial marketplace. Because our products offer specific blends of performance and energy efficiency, Freescale’s processors are well established within the aerospace and defense markets as well. Whether it is in flight controllers, graphic displays, or radar imaging, we’re involved in it all.

I understand that Freescale recently introduced its new QorIQ AMP Series. Aren’t they the processors with AltiVec technology reinstated?

BECK: Yes. We created a family of processors called QorIQ communications platforms, beginning with the P Series family, based on 45 nanometer process technologies. We have products that range from less than 5 W to a maximum of 30 W. Just recently, we announced the new QorIQ AMP Series products, based on 28 nanometer technology. This new family of QorIQ AMP processors is a continuation of multicore processing platforms introduced as QorIQ communications platforms. Clearly, the use of many-core microprocessors is how the industry can deliver more performance within embedded power envelopes. Freescale’s trust architecture is also designed into the AMP processors, providing the ability to securely boot up the device, provide domain separation, and detect external threats to one’s system. In addition, the AMP series has reintroduced AltiVec technology, which is available on our new e600 core. AltiVec is used in aerospace and defense applications as a signal processor within a control/communications processor. It is well adapted in radar and graphics display imaging – basically, in any signal processing application.

Okay, let’s talk AltiVec technology for a moment, which has been a hot topic in a lot of the discussions I have been sitting in on. AltiVec went away for a while, and now it’s back in this AMP Series processor. What was the impetus?

BECK: Right, so everybody remembers that AltiVec technology was first introduced in the MPC7400 series processors. That core later became known as the e600 core when it became part of a System on Chip (SoC) platform. The first introduction of the QorIQ family used the e500 core, which didn’t include AltiVec technology. There is no doubt that the aerospace and defense market has had strong adoption of AltiVec technology for many years, and frankly it was missed by this market. But over the past three to four years, we have seen an increased demand and requirement for SIMD-like performance in other markets outside aerospace and defense. Like a lot of companies, we are market- and customer-driven and we began to see a need for AltiVec in the telecom, networking, video surveillance, and medical imaging spaces, to name just a few. As those appeared, we knew it was appropriate to bring this technology back to the QorIQ family of processors. That reintroduction has occurred in the recently announced QorIQ AMP T4240 product.

Looking forward, do you think all of your processors will have AltiVec on them?

BECK: As far as I can see for the foreseeable future, there is no reason for us to not include the technology in our QorIQ products. In fact, I think we expect constant improvements in the future.

Are there any specific road maps for improving AltiVec?

BECK: None that I can speak to at this time; however, many choices will be available to customers. If you remember, we first introduced AltiVec in the MPC7400. Then in about a year and a half, there was an MPC7410. And in another year and a half, there was an MPC7445, and on and on until we came to MPC7448. So about every year and a half we would have a new device with AltiVec technology incorporated, delivering ever-increasing performance. With the QorIQ AMP series, one can expect to see a number of devices across the T1 to T5 series over the next 12 to 24 months. This will provide customers more choices across a broad range of power, performance, and cost and greater alternatives for all kinds of applications.

Earlier you mentioned the AMP Series facing challenges of more performance in power envelopes and security issues. Let’s address those.

BECK: Whether it is the soldier on the ground or in the plane in the sky, the amount of voice, data, and video processing required is rising astronomically. In addition, more systems are becoming unmanned, whether they are aerial or ground vehicles. These UAV systems are requiring ever-increasing sensing capability for growing data analysis. The result is a need for more autonomous real-time decision capability at the point of data collection. This translates directly to the need of more processing capability within very demanding power (heat) envelopes.

Classically, the way we have provided better performance is by decreasing the size of transistors, which means you’re able to switch transistors quicker and therefore deliver more frequency. We complement this with increasing performance through system functionality. We have moved from PCI at 66 MHz to PCI Express interconnect at 1 and 2.5 GHz and PCI Gen2 at 5 GHz and are moving from DDR1 to DDR3 memory controllers. All of those help system performance. I do not know about you, but it seems this transition has occurred in such a short period of time. At Freescale we design SoC microprocessors that balance performance across cores, memory, and I/O subsystems in a single device at particular embedded power envelopes (Figure 1). This platform strategy provides customers alternatives to get the maximum performance for their applications.

 

Figure 1: Road map depiction for Power Architecture devices

(Click graphic to zoom by 1.9x)

 

The other way you increase system performance is by increasing the frequency and the number of cores. Of course, the challenge associated with this is increased power and heat. We designed the QorIQ platforms devices within designated power envelopes. For example, the P1 family is a 5 W envelope, P2 is 10 W, P3 is a 15 W envelope, and P4 and P5 devices are 30 W envelopes. All these P series processors are 45 nanometer products.

Those are the original QorIQ processors, but can you give a technical example of this improved power envelope for the AMP Series?

BECK: As a design philosophy we balance SoC devices that utilize cores, hardware accelerators, memory, and I/O subsystems. The T4240 uses the new e6500 Power Architecture core. This 64-bit core is dual threaded, with L1 and L2 cache and also contains the 128-bit AltiVec unit. These cores connect inside an SoC platform via a coherency fabric that allows us to create point-to-point connections between I/O, accelerators, and memory subsystems resulting in high-performance processors within embedded power envelopes. We take advantage of hardware accelerators to offload work on cores, which allows us to accomplish work with fewer transistors, translating to lower power. Examples of those hardware accelerators are security engines and pattern-matching engines. As we move from the P4080 device to the QorIQ AMP T4240, we are delivering more performance per watt than previously realized. Benchmarks are demonstrating a 4x performance – pretty exciting stuff.

Where do the higher speeds come from?

BECK: The industry always speaks about improved speed, but it’s really about improved performance. But first, let’s address the speed. As has been done for more than 20 years, we get improved frequency with improved process geometries. We had improvement in frequency as we went from 1.5 GHz up to 2 GHz as we moved from 45 to 28 nanometer technologies while maintaining the same pipeline architecture. Additional performance improvement resulted from increasing the number of cores from 8 to 24 virtual cores. And we provide significant floating point performance with use of the AltiVec unit where the T4240 is capable of generating 192 GFLOPS.

Let’s move on to the security you mentioned earlier – where does that fit into the AMP Series of QorIQ?

BECK: I use an acronym that is applicable to the A&D market. The addition of a capital “A” to “SWaP,” which makes it “SWAaP.” It’s about adding “Assured computing” to the long-held requirements related to Size, Weight, and Power. And it has become another critical component to every system. Every A&D RFQ or RFI has a secure or assured component. The delivery of that component cannot jeopardize the performance requirement of the mission. All future systems must be capable of withstanding security attacks. Those attacks come in the form of:

1) Theft of functionality: When someone is able to take over that system and cause it to act in ways that it wasn’t intended to behave.

2) Theft of uniqueness: OEMs spend millions of dollars and years of development of systems. To see those investments efforts be reverse engineered can be disastrous.

3) Theft of Data: Loss of one’s IP or data that is stored on the device to unauthorized parties.

How are these challenges mitigated in the AMP Series?

BECK: We created our trust architecture capability in the P series product and have extended it in the AMP series. The primary features are secure boot, domain separation, tamper detection, and secure debug. In terms of a secure boot, you want to know that your bootable image is trusted and has not been tampered with. So, we provide the user the ability to put a secure key fused into the device. The boot process begins within the walls of your factory. With a private key, you create a 256-bit hash signature of your known trusted image. During the secure boot process, you create a signature with the key you have stored on the processor and validate that signature to the image while booting the processor. If validated, the processor is brought up in a trusted state.

Once in a trusted state, you can then begin the process of creating domain separation of cores, memory, and I/O devices. In other words, you want to distinctly define a particular relationship between cores, memory, and I/O devices in a defined partition. Domains are now able to operate independently without fear of corruption. We have intentionally designed the capability into the processor to ensure that domains are separated in the way the user wants them. This allows customers to provide separation between public, confidential, and secret regions.

Trust architecture also has the ability to react to physical threats to the system. The types of attacks are defined by the OEM. Some may be as simple as opening up a cabinet door. When this happens, a signal is sent to the processor and it immediately begins to zeroize the memory regions of the device. The device is now unusable and can only be made whole again through the secure boot process.

What about network attacks?

BECK: The way we prevent network attacks is decided by the user’s security policies during the secure boot process though the partitioning of the cores, memory, and I/O. Each partition is identified with a unique logical address. Network attacks come in the form of when someone will attempt to insert harmful instruction code in a particular memory region to gain control of a device’s functionality. Network packets must begin authorization through a secure tunnel to the partition. Unauthorized requests are prevented from accessing a partition. A security monitor notes these attacks and notifies the OEM.

In addition, one must be able to have access to the system once it is deployed in the field. One is able to securely debug a processor, provide software upgrades, and change security policies while the system is in the field. This is done through a debug port that is entered via a question/answer handshake that the OEM has created and stored in the processor.

In the past, these types of security features [secure boot, threat detection, secure debug, and domain separation] have been external to the processor by FPGAs, TPMs [Trusted Platform Modules], or even custom devices. We have put these features inside the QorIQ processors. It has the benefit of increasing security by fewer devices and exposed buses. In addition, it decreases the overall system cost.

Is the trust architecture user-friendly, or is it complex to navigate?

BECK: We believe we have made the implementation of the trust features user friendly. But implementation of the trust architecture is a big commitment for the user. If you ever lose your private key, it makes those systems unusable. It is a user-defined option. If you choose not to put it in trust mode, then you can use it as any processor is used today.

One last question: What is needed now in your arena, but not available now?

BECK: It is interesting to me that there was a real fear about how quickly multicore processing would get adopted. While there is considerable need for improved software tools, the adoption has been extraordinary. The ever-increasing demand for performance within stringent power envelopes has resulted in a broad spectrum of applications. It is clearly the path we are all taking. We have just begun to deal with the challenge of certifying multicore systems in commercial aviation. While challenging, it will happen.

In addition, the fundamental challenges of system design remain: latency, bandwidth, and power. I know here at Freescale, we are constantly working to solve these real-world problems. Frankly, it’s lots of fun.

Glenn Beck is Market Segment Manager for the Network Products Division, Freescale Aerospace and Defense/Single Board Computing Market. He is a 32-year semiconductor veteran with Motorola/Freescale. His experience has been in design and product engineering, and he presently leads Freescale’s marketing efforts in A&D and single board computing with Power Architecture microprocessors. He holds a BS in Electrical Engineering from Texas A&M University and an MBA from Texas State University. He leads the Multicore for Avionics (MCFA) working group of avionics suppliers in an effort to certify platforms with multicore processors. He can be contacted at [email protected].

Freescale Semiconductor 512-996-5043 www.freescale.com