COTS vendors step up to new multicore processorsStory
September 23, 2009
Multicore devices have been on the market awhile, but they are not yet widely used in real-time embedded applications. However, the desire for improved performance with less power in a smaller package is driving new multicore device designs.
Although multicore devices have been available for some time now, their use has not yet become widespread in real-time embedded applications. Multicore devices such as Intel’s Core2 Duo and Core2 Quad are widely used in desktop and server applications. However, the number of cores available or in use is made transparent to the users by the operating system. In contrast, an embedded system must execute predictably within deadlines that at times require the full use of all available resources. This is most easily proven by just using a single dedicated processor with its own I/O and memory resources. Yet the potential for significantly greater performance in a smaller package and with less power consumption is sufficiently attractive to drive the design of new multicore devices.
Freescale Semiconductor QorIQ
The real-time military embedded market is dominated by Freescale Semiconductor’s Power Architecture processor family. It includes a diverse application base ranging from ground-based combat vehicles, C2 and C4I, to avionics and flight control. For its next generation of devices, Freescale chose its e500 Power Architecture core, with up to eight cores arranged symmetrically on a single device. There is a range of devices in this new family named QorIQ (pronounced “Core-I-Q”), aimed at a broad spectrum of applications. At the high end, the P4080 is designed to dissipate no more than 30 W with eight cores operating at 1.5 GHz. This makes it ideal for high-performance yet space-, weight-, and power-constrained embedded applications, offering interesting architectural possibilities for efficient core utilization. The eight-core P4080 block diagram is illustrated in Figure 1.
Figure 1: The eight-core P4080 block diagram
(Click graphic to zoom by 1.9x)
Each core has 32 kB L1 instruction and data caches plus its own 128 kB L2 cache. The architecture supports independent execution of each core, with separate user and supervisor modes. In addition, a hypervisor running as a microkernel on each core plus a secure memory partitioning model provide many of the functions needed to support either Symmetric Multiprocessing (SMP) or Asymmetric Multiprocessing (AMP). This use of secure memory partitions naturally makes QorIQ suitable for trusted platform applications such as Multiple Independent Layer Security (MILS). An on-chip fabric connects the cores with L3 caches, external memory, network support including 2x 10 GbE (XAUI) ports, PCI Express (PCIe), and Serial RapidIO, now commonly used as a low-latency fabric in multicomputing sensor processing systems.
Migrating to multiple cores
New projects and the migration of existing Power Architecture applications can benefit from the flexibility of eight processing cores. Conventionally, real-time systems will dedicate functions and tasks to individual cores because this will provide more easily verifiable operation, particularly where timing deadlines are crucial. This model allows the migration and physical contraction of many existing applications from multiple SBCs to a single SBC – subject to review of a system’s I/O requirements – while maintaining a high degree of software compatibility.
New applications might feature the AMP model partitioned differently, perhaps using one core for I/O, one for networking, and others for individual functions. Where a surplus of cores exists, one might also be allocated to online prognostics, self-test, and diagnostics. Using all eight cores in a dynamically scheduled SMP environment will require specialized software tools like those developed for multicomputing DSP systems that instrument and verify a system’s performance. Similarly, the extension of today’s multicomputer DSP tools to graphically visualize architecture, assess performance, and allocate tasks will merge the distinction between multicore and multicompute development environments and configurations.
Embedded product plans
Plans to support various versions of QorIQ with environmental options for military applications have already been announced by board-level COTS vendors such as GE Fanuc Intelligent Platforms. In addition to top-end, high-performance products based on the eight-core P4080 device using the 6U VPX (VITA 46) format, SBCs have also been announced in 3U VPX and 3U CompactPCI formats using the dual-core P2020. This is anticipated to offer comparable performance to existing products based on Freescale’s 8641D but with lower power consumption.
There will still be much debate on the future shape of applications for multicore Power Architecture. But it is clear that the QorIQ family of devices re-establishes the MIPs/Watt position. Additionally, software compatibility is maintained for legacy migration, and major board-level COTS vendors are firmly committed to future product development. Whether AMP, SMP, or a mix of processing configurations will predominate remains firmly in the hands of future users and systems integrators.
To learn more, e-mail Duncan at [email protected]