Structured ASICs: A clear advantage when designing advanced military and aerospace electronics
StoryNovember 11, 2008
Barry West
ON Semiconductor
Today's military and aerospace electronics face challenging environments as well as increased security and production handling requirements, and must adhere to stringent reliability specifications while fitting an effective business model. Three custom logic options exist - FPGAs, traditional cell-based ASICs, and structured ASICs. But structured ASICs offer clear advantages over their competition.
The advanced capabilities of military and aerospace electronics available today can be clearly seen in the improved performance, efficiency, and safety of new commercial aircraft. These capabilities have changed the way soldiers fight the war against terrorism. A primary contributor to the advancement of these next-generation applications is the complexity of the electronic systems used to design these leading-edge and increasingly autonomous systems. Just like the designers of consumer or telecommunications electronics, mil/aero product designers need access to advanced deep-submicron process technologies to meet the specifications of future products. In addition, they need access to complex IP such as microprocessors and DSP cores, as well as high-performance memory and serial interfaces.
Mil/aero designs often have special requirements that make them more difficult than commercial applications, posing unique problems to system designers. Challenging environmental conditions, enhanced security and production handling requirements, and stringent reliability specifications contribute to the complexity of design and limit the choices of which technologies and IP can be used. Additionally, mil/aero electronics are difficult to fit into an acceptable business model as they are usually low-volume applications, making it difficult to justify very expensive technology tooling costs for cutting-edge process technologies and large licensing fees for advanced IP.
There are three options for a systems designer who needs to implement custom logic in a mil/aero electronic application: FPGAs, traditional cell-based ASICs, and structured ASICs. We'll review each option and detail why structured ASICs offer clear advantages over the others (Table 1).
Table 1
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Are FPGAs a fit for mil/aero applications?
At first glance, FPGAs appear to have compelling advantages for logic solutions in mil/aero applications. The latest generations of these programmable devices offer impressive performance capabilities and come with an extensive library of embedded and soft IP functions. Advanced IP like microprocessors and memory interfaces available in these devices make them attractive for avionics applications. The advanced IP and in-system reconfigurable logic seem like an ideal match for Software-Defined Radio (SDR)-based communication systems, which need high performance and the ability to change hardware configurations during operation.
These capabilities also add value in many different military applications such as smart munitions, cryptography, and battlefield electronics such as night vision goggles. FPGAs can be bought in limited quantities and don't have non-recurring engineering charges, which contributes to reduced product and development costs. All of these factors are important to mil/aero system providers. However, when looking deeper into additional requirements of mil/aero applications, the match between these systems and FPGAs is not as good as it might initially appear.
In avionics applications for both the commercial and military sectors, flight-critical electronic devices are exposed to higher levels of neutron radiation, which can cause Single Event Upset (SEU) issues on small process geometry RAM elements. These, in turn, typically cause a temporary stored data loss in a memory device. This effect is of particular concern in SRAM-LUT-based FPGAs, where logic configuration data is stored in RAM elements. Configuration data upset in the RAM-based LUT can potentially result in a device-level logic error. This phenomenon has been a well-known consideration in avionics applications for more than a decade. FPGAs also require from 500 ms to 800 ms at power-up to facilitate programming a mid-sized advanced FPGA into its functional configuration. This can cause concerns in the case of system power-down or reboot during flight. These issues make SRAM-based FPGAs a very poor, and in many cases, forbidden, match for flight-critical applications.
A military radio based on SDR electronic systems needs to be carried into battle and function for many hours or days on battery power. This means these systems must be as light as possible and be very efficient for dynamic and leakage power consumption. Even though FPGAs meet the need of configurable logic and advanced IP for these devices, they also consume large amounts of static and dynamic current because of their LUT-based logic structure. The ability to have fully reprogrammable logic means inefficient structures that draw a lot of power during operation. The complex FPGAs used in these applications can consume 6 W of power or more in cases where large amounts of logic are used and high performance is required.
Certainly, a degree of in-system reconfigurable logic is required to implement goals of dynamic waveform generation, but the degree to which FPGAs are relied upon in current radio architectures drives current radio designs well out of acceptable ranges for power budget and form factor requirements. Again, the special requirements of these systems make complex FPGAs a poor fit in meeting the full operational requirements of the system. This is true for all battery-operated devices including night vision goggles, as well as other communication systems.
Security is also a factor in all military applications, and FPGAs are inherently susceptible to security intrusion because they require off-chip ROM or processor loading to store the logic configuration bit-stream information. Despite advances in encryption techniques, this data is still easily compromised by hostile forces and can be used to build equivalent hardware with little difficulty. Military applications also require special manufacturing handling such as ITAR support and/or NOFORN processing in U.S.-based manufacturing facilities. Nearly all of today's advanced FPGAs cannot support these requirements, as they are built outside of the United States in facilities that do not support special handling procedures. These factors limit the acceptability of FPGAs in mil/aero applications based on required standards of device security and assured production access, making them a non-ideal solution.
Expensive cell-based ASICs are difficult to justify
Cell-based ASICs solve many of the issues involved when using FPGAs. They can be designed for very low power and, by the nature of nonvolatile logic, have enhanced security and are live at power-up. There is also a wide variety of IP types available from many different vendors, supported at a variety of foundries. The best power, performance, and IP availability make cell-based ASICs an attractive technical option.
The associated trade-off with these semi-custom devices is that they are less cost effective for low- to mid-volume mil/aero applications requiring technologies more advanced than 130 nm. The cost to develop a custom 90 nm ASIC can range from $2 to $5 million when considering the high tooling costs, IP licensing and usage charges, and engineering development cost. It takes a significant amount of engineering resource to create and verify a design in 90 nm technology when typical complexity can include millions of gates of logic, several complex IP blocks, millions of bits of memory, and 500-plus I/O. It is not uncommon for a team of five to eight engineers to need more than a year to achieve tape out on a design of this complexity. And if anything is missed during verification causing silicon failure or if features need to be adjusted or added during prototype evaluation then the schedules are delayed even more and the costs continue to mount.
For mil/aero applications, cell-based ASICs using technologies 130 nm and larger can be a good fit. For 90 nm technologies and below, increasingly few military or aerospace programs can justify the expense and lead time required to develop cell-based ASICs for applications that will run in production volumes on the order of 50K units a year or less.
Structured ASICs meet the special needs of mil/aero applications
The structured ASIC was created to specifically address FPGA and traditional ASIC shortcomings and offers compelling advantages for system designers when compared to FPGAs and cell-based ASICs. Structured ASIC platforms also allow designers to have access to advanced technology nodes that offer the performance and IP portfolios needed for today's sophisticated mil/aero applications just like FPGAs and cell-based ASICs. But compared to FPGAs, the structured ASIC can be produced at mid to low volumes at significantly lower production costs. And compared to cell-based ASICs, the structured ASIC has much lower development costs because it shares tooling and IP licensing expenses across many devices and offers an optimized development span. This makes it a better fit for mid- to low-volume production.
The traditional fit of structured ASICs in the market is clearly shown in Figure 1, which includes the relative cost and span for each option. But beyond these traditional benefits, structured ASICs also solve many of the mil/aero system issues described in the previous sections. Consider the following military and aerospace applications and how a structured ASIC could meet the requirements for each.
Figure 1
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For battlefield communication applications such as a Joint Tactical Radio System (JTRS)-based SDR or any portable military device that will depend on battery power, a structured ASIC can be an effective fit. A structured ASIC platform that supports processing elements for General Purpose Processing (GPP) and DSP requirements as well as significant quantities of custom logic combined with standard interfaces such as DDR, LVDS, and Ethernet – is a good fit for these systems.
Consider the block diagram in Figure 2, which shows an SDR system architected using a large structured ASIC that can handle the high-performance algorithms common across all JTRS waveforms, combined with a smaller FPGA to handle the reconfigurable needs of these systems. An architecture such as this can use up to 10x less power than a system built out of multiple large FPGAs, which is common in the current generation of SDR systems. This is because the structured ASIC architecture uses ASIC-like logic structures and libraries that are significantly more power efficient than FPGA LUT-based logic while still giving high performance. Smaller devices, much lower power, and a greater degree of physical security all lead to a system more in line with form-fit-function program objectives.
Figure 2
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For an application that has cryptography requirements or other security concerns (such as military communications) or any application that could be a target for enemy tampering, a structured ASIC can be an effective solution. The structured ASIC does not need a discrete device to provide a bit stream that is required to program an FPGA device. A bit stream is relatively simple to tamper with and decipher, and once hostile forces have it, they can program equivalent devices with little difficulty. If a structured ASIC also contains an embedded battery-backed memory device such as Security Enhanced XPressArray (S-XPA) from ON Semiconductor (formerly AMI Semiconductor), then cryptography and antitamper IP such as AES encryption engines or secure key processors can be added to a system with the keys stored in a secure on-chip memory. This increases security levels and makes hostile tampering or reverse engineering more difficult in any sensitive military application.
In the case of avionic electronics such as flight-critical control applications, a structured ASIC can meet the requirements of systems where dependable operation is crucial. Access to a cost-effective solution that provides high performance and advanced IP but also meets reliability requirements for SEU performance and live on power-up technology gives the aerospace electronics designer a significant advantage. The structured ASIC platform can support IP such as microprocessors, standard interfaces such as PCI and Ethernet, and error detection and correction algorithms while providing for plenty of RAM and custom logic to implement any proprietary functions needed for these applications. Combine that with high reliability and low cost and you get a solution that is ideally suited for these applications.
Specific to the types of low-volume and low-cost applications predominant in the military and aerospace industry, the structured ASIC is a much better overall solution when compared to a cell-based ASIC. Structured ASICs have lower hardware costs because only a few custom masks are needed to program the base-level silicon into the specific device. And even though the design flow for a structured ASIC is similar to a custom ASIC flow, it can be more efficient by relying on pre-verified and embedded IP that is already qualified and proven in the technology being used. Devices like the XPressArray family from ON Semiconductor are manufactured in the United States and support full on-shore design, manufacturing, assembly, and test flows to meet special handling requirements for sensitive military electronics.
The most benefits for military systems
The benefits of structured ASICs for military and aerospace systems are growing increasingly clear. They go beyond the immediately tangible power and cost benefits compared to FPGAs and the development cost of custom ASICs to include more specific benefits of enhanced security, improved reliability in harsh operating environments, and the ability to meet the "trusted" manufacturing requirements of military applications. Accordingly, using structured ASICs that allow for on-shore manufacturing and include the required IP enables suppliers of military and aerospace electronics to build applications that meet the special requirements of this market.
Barry West is principal systems architect, mil/aero and digital products/services at ON Semiconductor. He is responsible for working with customers to define system architectures to meet their system requirements and for defining product roadmaps for mil/aero applications. Additionally, he is an expert in many EDA design tools including synthesis, STA, and physical design and verification. He can be reached at [email protected].
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