VPX standards keep pace with faster fabrics

Story

October 12, 2011

High-speed fabrics driven by the commercial market are also revolutionizing the military embedded market, by way of the VITA 46, 65, and 68 open standards - which aim to keep VPX on track to deliver the ever-increasing need for speed.

VME has been the dominant bus architecture for the embedded market since its inception in 1981, and for the defense and aerospace portion of that market since the late 1980s. From 1981 to 2003, performance has increased eightfold from 40 MBps to 320 MBps. The performance increases came through architectural improvements, but fundamentally, clock speed remained the same. Today, with VPX and its ability to support serial fabrics such as PCI Express (PCIe), Serial RapidIO, Gigabit and 10 Gigabit Ethernet (GbE), and InfiniBand, there is a continual push to ensure that the backplane has the speed and bandwidth required to support the next, fastest variant of these fabrics.

Additionally, fabric speeds are increasing at a fast pace, driven by the commercial market. And the change is happening at a faster rate than was seen in the past. Ethernet, PCIe, and Serial RapidIO are all migrating to faster speeds, in part driven by the processing infrastructure being developed to support cloud computing and the so-called “Internet of Things.” As even the most mundane devices become connected to the Internet, the amount of data the Internet backbone needs to handle will continue to grow rapidly. While the military market is too small to be a market driver for serial fabrics, it is positioned to benefit from the resulting performance improvements.

The increase in fabric speeds is impressive. The first VPX boards used Serial RapidIO at 3.125 Gbaud for transmit/receive pair. Today, VPX boards and backplanes are shipping with 5 or 6.25 Gbaud speeds. Figure 1 is an example of a standard Curtiss-Wright 6.25 Gbaud OpenVPX backplane; this one is 16 slots. In two to three years, it is anticipated that VPX boards will ship with 10 Gbaud speeds. In less than a decade, there will have been a 3x rate of speed improvement on the backplane serial interconnects.

Figure 1: 6.25 Gig OpenVPX backplane

(Click graphic to zoom by 1.9x)

To keep pace with this rate of change, open standards are evolving. We have seen PCIe go from Gen 1 to Gen 2 (5 Gbaud) and soon to Gen 3 (8 Gbaud). We’ve seen Serial RapidIO go from Gen 1 (3.25 Gbaud) to Gen 2 (5 and 6.25 Gbaud). The next variant of Serial RapidIO, Gen 10GxN (10 Gbaud) has been recently announced, with finalization expected toward the end of this year or the beginning of next year. On the Ethernet front, we’ve gone from 1 GbE to 10 GbE, which is now gaining prominence in our industry. 40 GbE is already starting to emerge in applications in the commercial space and, not surprisingly, military customers and vendors are starting to look at it, too. 40 GbE uses 10 Gbaud signaling, so it features the same physical SERDES signaling being used by 10GxN Serial RapidIO. Looking further out, 100 GbE is going to arrive in the next year and a half in the commercial space and will emerge some time after that in the military market. One version of 100 GbE uses 10 Gbaud signaling and another version uses 25 Gbaud signaling.

What does this all mean for VPX and OpenVPX (VITA 65)? There is plenty to be optimistic about, and a closer look at the VITA 65 and VITA 68 standards reveals just that.

Fitting in OpenVPX

The genius of OpenVPX is that it is not tied to a particular fabric technology or connector set. It supports multiple fabrics and speeds through the use of profiles. As newer fabrics come along and gain momentum in the marketplace, they can be added to the current list of fabrics already supported.

The same holds true for connectors. OpenVPX calls out VITA 46, which specifies the TE Connectivity MULTIGIG RT connector. However, there are already efforts underway to allow for the use of alternate VPX connectors, such as VITA 60 (Amphenol) and VITA 63 (Hypertronics). If a newer connector is required to take VPX beyond 10 Gbaud, then this could also be referenced in VITA 65. The challenge will be if this connector is not footprint compatible with existing VPX connectors. Today, the TE Connectivity, Amphenol, and Hypertronics connectors are footprint interchangeable, but not intermateable. That is, they use the same PCB footprint so a PCB can support all three connectors, but designers must use the same manufacturer on both the backplane and the module. It’s conceivable that a future pin-compatible VPX connector will be able to achieve 20 to 25 Gbaud per differential pair.

VITA 68 boosts channel compliance

The VITA 68 (VPX Compliance Channel) working group is dedicated to channel compliance or signal integrity. This working group is developing a new draft standard to define channel compliance for high-speed serial pipes over a VPX backplane. Initial simulations have shown that many protocols can operate at speeds up to 10 Gbaud using current VPX connectors. To support that effort, the VITA 68 working group has established a limited liability corporation with contributions from VITA member companies, including integrators, vendors, and connector manufacturers.

Initial plans include simulation and testing of the backplane channel at 1, 2.5, 3.125, 5, 6.25, and 10 Gbaud rates with channel parameters based on IEEE 10GBASE-KR, plus simulation of complete end-to-end channels including module Tx channels, backplane channels, and module Rx channels for several fabrics: Gen 1/2 PCIe for 2.5 and 5 Gbaud, Gen 1/2 Serial RapidIO for 5 and 6.25 Gbaud, and Ethernet for 1 and 10 Gbaud per differential pair. Future plans include simulation of Gen 3 PCIe for 8 Gbaud, Gen 3 Serial RapidIO for 10 Gbaud SDR, DDR, and QDR InfiniBand variants for 2.5, 5, and 10 Gbaud. Figure 2 shows Curtiss-Wright’s simulated 10 GBaud Insertion Loss to Crosstalk Ratio (ICR) for 10GBASE-KR, 10 GigE across a VPX backplane. This is one of several 10GBASE-KR signal integrity criteria being leveraged in VITA 68.

Figure 2: 10GBASE-KR VPX Insertion Loss to Crosstalk Ratio (ICR)

(Click graphic to zoom)

VITA 68 will specify several signal integrity parameters for different speed grades of backplane channels, using VPX connectors. This will allow a compliant backplane design to interoperate with compliant modules using various fabric types and different fabric speeds up to the rated speed grade of the backplane. The result of these simulations will inform users what to expect in terms of speed using the standard VPX connectors and connector 3D footprints. The simulations will tell which protocols will work best and how fast they will go over our current VPX backplane technology. And the simulations will show what to expect as speed is increased over the connectors and backplane to support the new fabric variants. Today, the lower-speed Gen 1 variants, up to about 3.125 Gbaud, work well. And no problems are foreseen in running Gen 2 Serial RapidIO and Gen 2 PCIe today if modules and backplanes are properly designed. But VITA 68 will ensure signal integrity interoperability as baud rates increase, and the simulations will lend understanding of what to expect as technology advances beyond Gen 2 rates to support upcoming Gen 3’s 8 to 10 Gbaud next-generation variants.

VITA 65 and 68 foster VPX signal speed

At this point in the development of the VPX standard and its ecosystem, it remains to be seen where the industry will end up in regard to connector types and fabric speeds. But, it is a safe bet that at some point, the industry will use optical connectors. When VPX was first defined, the original expectation of achievable bandwidth via the MULTIGIG RT connectors was 5 or 6 Gbaud. However, with careful design, layout, and routing, it appears that speeds up to 10 Gbaud are attainable with our current connector set. There was real foresight in the way that the VSO structured VPX and OpenVPX, enabling the addition of new protocols to VITA 65 as needed, once they’ve been successfully validated. That, along with the new channel compliance specification, promises to get us to 10 Gbaud signaling in the next several years.

Bob Sullivan is CTO – Engineered Packaging, at Curtiss-Wright Controls Electronic Systems. He can be contacted at [email protected].

Ivan Straznicky is a Technical Fellow at Curtiss-Wright Controls Embedded Computing. He can be contacted at [email protected].

Curtiss-Wright Controls Electronic Systems 978-952-2000 www.cwcelectronicsystems.com

Curtiss-Wright Controls Embedded Computing 613-599-9199 www.cwcembedded.com