Smaller form factors benefit electronic warfare applications
StoryApril 28, 2015
Lance Brown
Colorado Engineering, Inc.
Ching Hu
Altera
Small form factor (SFF) requirements continue to drive higher-performance computing platforms in electronic warfare (EW) and other signal-processing intensive applications year after year as there is an insatiable need for intelligence, surveillance, and reconnaissance (ISR). Airborne EW is a critical component of the military's overall EW strategy and almost all approaches desire more computational performance while reducing size, weight, power, and cost (SWaP-C) as more capabilities are added.
Smaller unmanned aerial system (UAS) platforms (for example, the Boeing Insitu ScanEagle or MH-6 Mission Enhanced Little Bird or the Northrop Grumman MQ-8 Fire Scout) are now performing EW missions alongside larger platforms like the General Atomics MQ-9 Reaper, the Northrop Grumman RQ-4 Global Hawk, and manned fixed-wing and rotary aircraft. Some platforms are not able to carry onboard the payloads of current processing technologies, so these smaller craft must download the data for ground-based processing.
(For more on these small platforms, see the Special Report by Sally Cole on page 16.)
Applications such as signals intelligence (SIGINT), digital radio frequency memory (DRFM), and radar processing for all aspects of EW (attack, support, and protection) are requiring more digital signal processing to achieve their goals, especially when they need to be adaptive with increasing bandwidth or are distributed.
This trend is unlikely to change even if the U.S. reduces its military footprint worldwide. Fewer boots on the ground means an even greater dependence on actionable intelligence from persistent ISR and EW systems.
Moore’s Law provides a basis for increased processing capabilities, but this does not imply that power consumption drops accordingly or that memory bottlenecks can be opened up. In some sense, a technological leap is necessary to allow the desired processing capabilities to fly on SWaP-constrained platforms.
Smaller boards for EW purposes
Algorithms that traditionally required a large, heavy box or ground-based system can now be performed on a small form factor board. In addition to the EW-centric applications mentioned previously, synthetic aperture radar (SAR), space-time adaptive processing (STAP), real-time spectrum monitoring and SIGINT, multispectral (MSI) and hyperspectral (HSI) image processing, communications link encryption, multiple channels of H.264/H.265 video compression, software-defined radio, and many other defense/intelligence-critical functions can be considered for onboard processing within small SWaP envelopes.
PC/104 answers the call
For meeting the magic sub-one-pound payload SWaP-C requirements of smaller platforms, PC/104 is an attractive and robust commercial off-the-shelf (COTS) standard with a rich assortment of existing I/O modules like Intel Core i7s and analog-to-digital/digital-to-analog converters (ADCs/DACs). The PC/104 form factor is just large enough for an FPGA plus one or two hybrid memory cube (HMC) memory chips, currently two or four GB each, and a variety of I/O interfaces.
FPGAs have become a game changer for signal processing systems such as EW and radar as they handle the front end, where the signals are received by the embedded computing system whether PC/104 or larger systems such as 6U VPX. The components are better connected to I/O than general-purpose processors and handle real-time processing more efficiently as well. In the end FPGAs essentially provide integrators with more control in their systems, enabling them with the flexibility pivot and modify their applications based on mission requirements.
For smaller form factors they are ideal. Add to that support for IEEE 754 Floating Point Unit (FPU) via Hard IP blocks and for OpenCL integration into the tool chain and the value of such a solution increases. The FPU is also a key enabler for OpenCL, which enables scientists, engineers, and researchers to program using the C language to massively parallelize their applications.
In addition to the standard PC/104 connector, a similar type of connector with custom I/O can be located on the opposite side to provide more I/O bandwidth if connecting to boards with mating connectors. Adding two peripheral boards containing high-speed ADCs and DACs can realize a full DRFM or general active sensor back end enclosed in a low-volume box.
Given the effective x16 PCIe Gen 3 bandwidth of 15.754 GBps in each direction, the data converter modules can transfer over 120 Gbps (e.g., 12-bit resolution at 10 GSamples/s [Gsps] or 16-bit resolution at 7.8 Gsps) and even more if a custom module can utilize the connector.
One recent example of a small form factor board comes from Colorado Engineering, the Arria Common Element PCI/104 (ACE-PCIE-104). The ACE-PCIE-104 features the 10AX066 with two to eight GB of HMC memory.
With the introduction of the some of the new powerful high-end field programmable gate arrays (FPGAs), such as the Altera Arria 10 and Arria 10 system-on-chip (SoC), many of these missions can be executed within smaller and lighter payloads. In case of this particular FPGA, it can provide as much as 1.5 TFLOPS and as much as a 65 percent drop in power consumption compared to a previous generation Stratix V, even with the embedded dual ARM cores of the SoC variant. When this increased performance per watt is married with HMC technology that provides 1.2 Tbps or 160 GB/s data rate, the possibilities expand. (See Table 1.)
Table 1: ACE-PCIE-104 interface data rates
(Click graphic to zoom by 1.9x)
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Other applications that could benefit from the ACE PCIE-104-CL SBC are scalable distributed aperture systems (DAS), situational-awareness 360 (SA360) systems, scalable ultra-wide band receivers, and small form factor EW threat generators. MES
Lance Brown is the director of High Performance Computing (HPC) at Colorado Engineering Inc. (CEI). Lance’s current work focuses on HPC for radar, electronic warfare, and cybersecurity systems along with smaller platform using FPGAs and GPUs for smart cities.
Ching Hu is a senior strategic and technical marketing manager in the Military, Aerospace, and Government Business Unit at Altera. Hu has been employed in the military and aerospace industry for more than ten years with roles in software and firmware engineering, program and engineering management, and military marketing. Hu earned his bachelor’s degree in optics at the University of Rochester, Rochester, New York.
Colorado Engineering coloradoengineering.com
Altera www.altera.com
