There are many COTS technologies available for implementing radar and sonar applications, including CompactPCI and VME, and newer switched-serial standards such as VPX and MicroTCA. By using real radar and sonar examples, the author illustrates how the communications topology can point designers toward choosing an optimal COTS architecture, in this case VPX (VITA 46) and CompactPCI.

Radar and sonar are mainstays and pervasive applications for military platforms worldwide. More recently, these Digital Signal Processing (DSP)-based systems provide a sophisticated foundation for missile defense – searching, tracking, and launching with great precision. System demands are increasing even further today, as systems must simultaneously locate and discriminate targets through tracking and identification to launch effective and appropriate countermeasures. At the same time, the Size, Weight, and Power (SWaP) of systems is required to decrease; for example, functionality previously implemented by 19" rack-mount servers installed in a pressurized wide-body aircraft must now be implemented in a ½ ATR on an Unmanned Aerial Vehicle (UAV). DoD requirements add to this growing challenge, mandating that systems are flexible and upgradable to respond to new threats and new applications. COTS-based systems gain an advantage here, as tech insertions to upgrade to the latest CPUs and communication technologies will be necessary during the lifetime of these deployed systems.

In response to this paradigm shift, depending upon the particular application, DSP-based radar and sonar systems can be achieved by using virtually every blade form factor available today; 3U/6U CompactPCI, VME, MicroTCA, or 3U/6U VPX can all be implemented with success. Additionally, contractors and manufacturers are responding to the latest challenges by offering a greater array of technologies for high-end DSP computing, including standards-based CompactPCI and VPX options. While high processing power is a common requirement, one COTS computing architecture does not fit all radar and sonar applications. It is usually the communication topology of the specific radar and sonar applications that suggests the optimal COTS computing architecture. Examples of CompactPCI and VPX illustrate this point.

Digital Signal Processing in action

The bulk of the computation in radar and sonar applications involves DSP. The essence of DSP is to efficiently transform a stream of data into relevant information quickly enough to be highly useful and applicable. In radar and sonar applications, for example, this may mean processing incoming electromagnetic or acoustic signals to determine the location, speed, and direction of potential threats, targets, and terrain while filtering out irrelevant data such as a small bird or fish.

Processing the data in an appropriate timeframe requires a high amount of computing power as well as the ability for each compute node to communicate with other nodes. The amount of processing and communication required is highly application dependent, varies widely, and likely increases with each tech refresh. But the topology of the communication is generally fixed, and that is the most likely discriminator in determining the best COTS architecture for a given application.

Figure 1 shows the communication topology of two real-world DSP applications. Each node in these topologies is a compute node, which is a sequence of transforms and filters implemented on one CPU node. The arrows represent data flow (communication), with darker arrows indicating higher bandwidths. For simplicity’s sake, only the higher-speed data plane communication is shown; each application also used GbE for control plane communication. Topology 1(a) was used for a sonar-based mapping application, while 1(b) was used for a high-end radar application for real-time use in theater.

Figure 1: Communication topologies of DSP applications range widely from (a) well-behaved pipelines to (b) high-speed hierarchical meshes.

(Click graphic to zoom by 1.5x)

For each communication topology, an appropriate COTS-based architecture was selected and implemented to meet the application requirements while still optimizing for SWaP.

CompactPCI meets the challenge in underwater sonar

The topology shown in Figure 1(a) for the sonar application reflects a typical “well-behaved” DSP application. The bulk of the communication is essentially a pipeline, with data flowing from one node to the next.

The digitized sonar data from the sensors is front-end processed by the left node, which then passes the data to a bank of three main compute nodes. Each of these implements a series of transforms for beamforming and filtering. The final node consumes all the data and synthesizes it into a spatial representation. The required bandwidth between nodes was less than 1 GBps in the main direction of dataflow [heavier lines in Figure 1(a)], with the backflow and control plane communication links requiring much lower bandwidths.

Given this topology, conduction-cooled 3U CompactPCI was chosen as the optimal COTS architecture for this application based on its small size and relative simplicity. Routinely considered a bus-based architecture, CompactPCI also supports multiple GbE communication links over the backplane, which was essential for this sonar application. Although originally implemented with dual-core processors, the COTS approach and a consistent pinout from generation to generation will allow this deployment to be extended, using multiple quad-core boards if and when higher precision is required for a technology refresh.

6U VPX for military radar

Conversely, the radar application’s communication topology shown in Figure 1(b) is much more complex. It requires many nodes, all able to directly communicate with each other at high bandwidths.

Sensor data is injected via high-speed links (>5 Gbps) in parallel to each six-node cluster. Within each cluster, a mesh topology allows the nodes to operate as a tightly coupled supercomputer, communicating with each other at >10 Gbps bandwidths. The clusters, in turn, require high-speed communication with the other clusters, also in a mesh topology.

The sheer number of high-speed data connections suggests that a switched-serial topology would be required, provided the data switches allowed enough bandwidth for all nodes to simultaneously communicate at full speed. VPX was a logical architectural choice because it allows for multiple high-speed interconnects; 6U VPX was selected specifically because its power envelope and Printed Circuit Board (PCB) real estate allow for two high-performance CPUs to be implemented in a single slot. Thus, each six-node cluster can be implemented with only three slots. This also makes the architecture scalable from a single six-node cluster in three slots up to 6 six-node clusters (36 CPUs in total) in 18 slots.

To handle the hierarchical high-speed communication topology, multiple data plane interconnect technologies were used. Within each cluster, PCI Express links provide high data throughput and a deterministic latency between CPU nodes. Between clusters, 10 GbE provides the required bandwidth and scalability. Figure 2 shows a simplified version of this as implemented on a 6U VPX architecture, including the aforementioned high-speed data plane links and the GbE control plane. Note that the architecture supports more connectivity than strictly needed to meet the requirements. Specifically, multiple 10 GbE links are available for each cluster, and nodes within adjacent clusters can directly communicate via PCI Express. These additional communication links currently go unused, but provide a valuable upgrade path looking forward.

Figure 2: VPX is used to implement Figure 1(b)’s high-speed hierarchical mesh, including three different communication interfaces.

(Click graphic to zoom by 1.5x)

A potential challenge of this type of VPX architecture is software complexity, resulting from the use of multiple high-speed serial communication technologies (PCI Express, 10 GbE, and GbE), each with a different software interface. Kontron VXFabric removes the complexity of these high-speed protocols by providing an API for a thin layer of software that allows IP-based data transport over PCI Express. As a result, from the software’s point of view, each interface looks like a high-speed IP socket, regardless of the underlying electrical implementation.

Determining COTS DSP approaches

It is important to note that both VPX and CompactPCI support multiple communication topologies beyond those highlighted here. However, a convenient rule of thumb is that complex board-to-board interconnect topologies with multiple high-speed connections tend to lend themselves well to a VPX implementation; applications with more “well-behaved” communications tend to use less complex and more pervasive technologies such as CompactPCI. Only careful analysis can determine the optimal COTS architecture for a given application. Specifically, the communication topology is the discriminating factor pointing toward one architecture or another. Regardless of the underlying architecture, the COTS approach will allow future upgrades and seamless tech insertions well into the future.

David Pursley is Product Line Manager at Kontron. He is responsible for business development of Kontron’s MicroTCA, AdvancedTCA, CompactPCI, VME, and VPX product lines in North America and is based in Pittsburgh, PA.

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