Mainstream IT-based HPEC technologies come of age
StoryDecember 10, 2014
Vincent Chuffart
Kontron
High-performance embedded computing (HPEC) is moving from the data center into the field of combat. Mainstream HPEC building blocks can reduce costs for these applications while providing ultrafast backplane speeds in a much smaller footprint and easily accommodating new proof-of-concept requirements.
High-performance embedded computing (HPEC) systems are seen as huge rack systems that are deployed to handle the most compute-intensive processing – such as command-and-control systems – that enable military personnel to see or detect ever-smaller objects in larger and larger fields. It seems that the increasingly advanced defense capabilities that can be achieved from the processing of multi-sense data show no signs of slowing down and seem to be limitless. Defense developers have typically gone the route of selecting specialized silicon for HPEC systems, primarily using FPGAs as the solution to deliver quick performance that can handle advanced electronic warfare algorithms and co-processing functions.
However, new HPEC solutions are evolving that are much smaller standards-based platforms – not the mega-computing platforms that we see deployed at present. Many new HPEC requirements that once called for highly sophisticated architecture can actually be satisfied with more compactly packaged mainstream IT technology. For instance, 3U VPX-based systems are available that balance I/O and CPU power with high-speed I/O backplanes and advanced multicore x86 processing architectures. These well-known platforms enable defense contractors to better control resources and costs while saving their most experienced engineering teams for large-scale, more complex systems or specific proprietary solutions that still require a higher level of design expertise.
The advantage of mainstream IT
Defense-system developers can realize many advantages by using mainstream IT HPEC solutions. First, developers can save on engineering resources because mainstream platforms don’t use specialty hardware, I/O, and switch fabric to qualify as an HPEC system. With extensive engineering experience with mainstream IT technologies such as x86 processors, TCP-IP, and the PCIe interface, this broader knowledge base can implement HPEC systems in end uses as disparate as laptops and high-end servers all the way up to conduction-cooled, ruggedized HPECs for ground control or even a UAV program. Developers can now tackle larger HPEC requirements that used to require specific proprietary solutions with well-understood architectures that are easier to program and deploy.
Proven technologies such as Intel multicore processors and PCIe 10/40 Gigabit Ethernet (GbE) permit a complete HPEC compute engine constructed of only standards-based components. For example, enabling specific-function FFTs for 3-D radar applications can be achieved through the co-processing capabilities with a GPU that the Intel architecture provides. Using such integrated standard-architecture technologies allows developers to eliminate extra design steps in order to offload certain functions.
The escalating data-processing demands from defense OEMs who request “all the performance you can give us” are now running up against the certainty of tightening budgets and the realization that new technology is not created or needed every year. Defense OEMs have learned to stay competitive by developing technology templates that can be used for multiple programs that work for three- to five-year life cycles. Without huge budgets and unlimited user support, defense contractors find that they are more profitable by not constantly supporting specialized silicon, language, and fabrics solutions. Adding to the problem: technology advancements are launched at an accelerated rate, preventing designers from continuously reimaging new architectures from scratch.
Commercial off-the-shelf (COTS)-based computing is the answer for proven building blocks and system solutions, with the algorithms needed already mapped onto the computing architecture. In addition, fewer OEM specialists are needed when HPEC suppliers can meet defense-program metrics by delivering the ultra-fast speeds they need on the backplane in a much smaller footprint. It also helps that COTS suppliers have the experience to accommodate new proof-of-concept requirements.
Leveraging cost-effective, accessible HPEC solutions
Modular and application-ready mainstream HPEC solutions help reduce costs by providing an accessible, easy-to-use, standards-based platform methodology. This proven approach supports a full range of military applications that include the gigabyte per second (GBps) performance needed for radar systems, all the way up to camera interfaces that require tens of GBps or five-plus teraflops, demanded by today’s 3-D radar.
Defense contractors can handle programs from the data center to field deployments by using smaller COTS multicore HPEC systems that can deliver a tenfold increase in I/O performance with no porting effort. Taking this simplified standards-based approach enables basic-skill-level engineers to meet high-connectivity and low-latency interconnect requirements with modular processor interconnect fabrics that implement the TCP/IP protocol over the PCI Express infrastructure. Going a step further, experienced HPEC suppliers give customers the option of building the computing portion of the application or supplying the right tools to facilitate a considerable system-size replacement. This can all be done with a couple of 3U VPX boards housed in a rugged, small chassis.
Mainstream HPEC system suppliers also have the knowledge to help with new proof-of-concept requirements. Contractors are able to rely on the suppliers’ valuable knowledge to speed complex application evaluation, benchmarking, and development to ensure the system will meet specifications including input rates, processing rates, and output.
Figure 1: Kontron VXFabric supplies the needed software between the PCIe Gen 3 switch and the bottom of the standard TCP/IP stack to enable boards to run any existing TCP/IP-based application without having to be modified. This interconnect fabric resource simplifies and helps propel application development of inter-CPU communication in VPX system architectures, enabling military OEMs to reduce development costs.
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Value-added HPEC tools
Value-added tools – such as those that enable users to easily access system-health status – have become a necessity due to continued technology advancements. One example of where this capability would be essential is the need to change clock speed to match battery demand in systems with x86 processor architectures. Varying clock speeds are unacceptable in military embedded systems that depend upon multiple computers and boards in which each board has a different clock cycle; differing clocks can result in an unstable power system. Health-management software tools that control speed and computing power are available today in 3U VPX box-level systems that integrate a computer-management board (CMB) (see Figure 1). These platforms give extensive system-health information at the board and sub-rack level such as controlling airflow temperature for each slot, and holding payload boards in standby mode to accommodate low-energy surveillance mode.
Today’s HPEC tools can also be used to implement more realistic lab testing that simulates the stresses and environmental conditions under which a system will be deployed. Proving a simplified methodology for testing new ideas is important, and mainstream TCP/IP streamlines the process from the lab to deployment with the same technology. No one wants to get to the last stage of development and integration, only to find out through actual environment testing that the algorithm doesn’t perform to mission standards. Integrated software tools are also invaluable when designing the power-management portion, considering a typical users’ guide for a current chipset dedicates 12 pages to defining power-management guidelines (see Figure 2).
Figure 2: Kontron’s VXControl permits detailed out-of-band system monitoring and control of critical signals at the computer level. It handles computer control and health management for a full range of functions that extend from the serial line interface to SNMP networking connections.
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A new age of mainstream HPEC is here
Satisfying application requirements for HPEC no longer requires complex, huge platforms. Rather, new HPEC solutions have been evolving steadily that can handle most high-performance computing tasks in much smaller 3U VPX standards-based platforms.
Today’s 3U VPX systems employ high-speed switched PCIe and 10 GbE on the backplane, making it far less appealing to use proprietary architectures when these multiprocessor and highly integrated HPEC systems are available to meet defense-program performance and bandwidth specifications. In addition, using modular pre-integrated HPEC solutions ensures design flexibility and longevity. HPEC platforms also feature customization options so system designers can satisfy multiple program-specific requirements. This modular approach more easily accommodates future system upgrades, eliminating the need for a total system redesign.
The use of standard communication protocols enables developers to protect their application software investments. Mainstream VPX-based HPEC platforms have already been proven to meet size, weight, and power (SWaP) demands while also satisfying the need for higher performance and bandwidth. Incremental defense program improvements can now bring new opportunities for smaller HPEC machines that can definitely handle almost any high-performance computing task put before them.
Vincent Chuffart is Senior Portfolio Manager for Kontron’s Military, Avionics, and Rail business unit. He has more than 25 years of experience in computer software and hardware development, encompassing several generations of embedded computers and parallel-signal-processing architectures. Before the Thales Group was acquired by Kontron, Vincent led the Thales embedded computing group before moving into product management. He holds an engineering degree from the Institut superior d’electronique du Nord in Lille, France.
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