HPEC radar processing architecture meets goals of USAF next-gen radar study
NewsMarch 10, 2016
ASHBURN, Va. The U.S. Air Force completed the Next Generation Radar (NGR) Processor Study. The results demonstrated that Curtiss-Wright?s proposed multiprocessor High Performance Embedded Computing (HPEC) Radar processing architecture has met the study?s target benchmarks.
The purpose of the study was to assess the performance ability of airborne radar signal processing with commercial-off-the-shelf (COTS) hardware and software. During the study, Curtiss-Wright engineers tested current generation as well as future next generation OpenVPX modules.
The analysis included meeting Synthetic Aperture Radar (SAR) and Ground Moving Target Indicator (GMTI) standards on a solution comprised of the OpenHPEC Accelerator Suite development tools, five OpenVPX DSP modules, and a 40 Gbps OpenVPX Ethernet switch module.
Each benchmark is designed to leverage advances in commercial high performance computing (HPC) software. Test results also demonstrated that standard conduction-cooled OpenVPX modules could be used to satisfy the performance requirements to support the SAR and GMTI standards.
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