DARPA's Electronics Resurgence Initiative addresses eventual saturation of Moore's Law
StoryOctober 05, 2017
In an effort to address Moore's Law before engineers run out of time, Defense Advanced Research Project Agency (DARPA) officials recently launched the Electronics Resurgence Initiative (ERI). The initiative consists of six programs in which engineers from government, industry, and academia, will spend the next four years scrutinizing the three pillars of the program - materials and integration, circuit design, and systems architecture - to ensure that technological progress continues at the same rapid pace. Moore's Law - the prediction that the number of transistors in a dense integrated circuit doubles approximately every two years - has held true in the microelectronics world over the past five decades. Now, however, engineers realize that the fast clip of technological innovation will eventually outpace Moore's Law.
In an effort to address Moore’s Law before engineers run out of time, Defense Advanced Research Project Agency (DARPA) officials recently launched the Electronics Resurgence Initiative (ERI). The initiative consists of six programs in which engineers from government, industry, and academia, will spend the next four years scrutinizing the three pillars of the program – materials and integration, circuit design, and systems architecture – to ensure that technological progress continues at the same rapid pace. Moore’s Law – the prediction that the number of transistors in a dense integrated circuit doubles approximately every two years – has held true in the microelectronics world over the past five decades. Now, however, engineers realize that the fast clip of technological innovation will eventually outpace Moore’s Law.
Before DARPA rolled out its ERI, Dr. Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO), and other DARPA representatives spent the summer of 2017 speaking with representatives from private commercial industry. The results of the research and investigation pushed MTO to launch ERI. DARPA officials realized the potential of working with industry alongside the Department of Defense (DoD) to innovate in the area of national security, Chappell says.
The growing complexity of systems has undoubtedly pushed DARPA and industry to think way ahead of the game: Because of the pace of innovation and style of corporate product development, says Chappell, it has become hard for the DoD to keep up with trends in design and manufacturing. The ERI wants to address the current issues with Moore’s Law from design concept to physical products.
ERI builds on years of experience and past programs that also address the three pillars of materials, circuit design, and systems architecture. For this specific initiative, DARPA is taking it a step further with its university-based program: Joint University Microelectronics Program (JUMP), which DARPA says intends to “build up a fundamental research base in fields underlying microelectronics technologies.”
DARPA wants to ensure that this initiative is successful: The Broad Agency Announcements (BAA) posted calls for a $75 million per year investment to overcome the current challenges and eventually create the autonomous, intelligent systems that are currently out of reach.
The systems architecture pillar will encompass the Software-Defined Hardware (SDH) and Domain-Specific System on a Chip (DDSoC) programs, both of which address the concerns around big data. SDH, especially, wants to find the most efficient way to get more data in a network, Chappell explains. In a similar vein, the DDSoC aims to revolutionize how systems recognize the type of data in use and reconfigure themselves as needed in the moment.
The Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program will fall under the circuit design umbrella, while the materials and integration pillar houses the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program and the Foundations Required for Novel Compute (FRANC) program.
The following provides a small glimpse into each. For more information, visit the DARPA website (www.DARPA.mil).
- Three Dimensional Monolithic System-on-a-Chip (3DSoC) program The aim is to develop design tools, materials, and fabrication techniques in order to build “microsystems on a single substrate with a third upward dimension, compared to the usual flat, two-dimensional format for microelectronic chips,” DARPA says.
- The Foundations Required for Novel Compute (FRANC) program FRANC aims to transcend the traditional von Neumann architecture, which throttles performance because it cannot simultaneously perform both an instruction fetch and data operation. DARPA states that “those submitting research proposals for this program will need to show how they might overcome this ‘memory bottleneck.’”
- The Intelligent Design of Electronic Assets (IDEA) program IDEA wants to take the human out of the equation. The end goal will be to enable a nonexpert user to design complex electronic technologies.
- The Posh Open Source Hardware (POSH) program Alongside IDEA, POSH wants to “deliver an open-source design and verification framework, including technologies, methods, and standards, which would enable cost-effective design of ultracomplex SoCs,” according to DARPA.
- Software Defined Hardware (SDH) program DARPA says that the goal of this program is to develop a “decision-assistance technology base for designing and manufacturing reconfigurable hardware and software that can run data-intensive algorithms.”
- Domain-Specific System on a Chip (DDSoC) program The program seeks to “develop multi-application systems through a single programmable framework,” according to DARPA documents.
For more information on the ERI, visit the DARPA website at www.darpa.mil/news-events/2017-09-13.
