COTS vendors speed FPGA development cycle
StoryAugust 14, 2009
John Wemekamp
Curtiss-Wright
FPGAs' complexity and inherent flexibility necessitate prequalified tools, IP components, and a coherent development framework to keep tight project control. Consequently, COTS vendors are rising to the challenge of developers' maturing expectations by continuously improving toolsets and product integration.
Although FPGAs are now used for DSP in many very diverse applications, they have become indispensable when parallel and repetitive algorithms are required by surveillance, Signals Intelligence (SIGINT), and Electronic Counter Measures (ECM) applications. In military guise, often operating over extended environmental ranges, these applications require the high channel count, I/O bandwidth, high performance, low latency, and small size that only an FPGA-based product can provide. However, the complexity and inherent flexibility of today's devices require prequalified tools, IP components, and a coherent development framework to keep tight project control and achieve realistic time-to-deployment goals. COTS vendors are rising to the challenge of developers' maturing expectations by continuously improving toolsets and product integration.
The case can be so strongly made in favor of using FPGA-based technologies for military sensor processing that the key decision point is now between using internal resources or buying off-the-shelf. Decision makers should weigh factors including time-to-market, the availability of the necessary in-house skills, the cost of training, and the level of risk. Additional consideration should be given to the potential return on investment, which might be measured in size, weight, or power saved, reduced recurring cost, selling in greater quantities, or enhanced competitive differentiation. However, in the defense and aerospace market, production volumes are often small with limited opportunity for direct reuse elsewhere, highlighting the need to keep development cost and risk to a minimum.
Integration
Because of its many benefits, the FPGA can become the focus of attention when selecting the sensor's overall architecture. It is relatively straightforward to visualize, simulate, and scale the DSP problem to the proposed sensor application using high-level tools such as The MathWorks' Simulink. But equally important is integrating the FPGA with the overall system environment: data acquisition, buffering, internal/external memory control, data path bandwidth, results dissemination, synchronization, error recovery, fault reporting, instrumentation for test and verification, and, finally, proof of operation over the platform's temperature extremes. This mix of internal, external, and interface issues to be resolved will require close integration of tools, libraries, I/O modules, and vendor-supplied IP. When forming part of a heterogeneous processing system, an FPGA must also be integrated with other processor types using common I/O, data structures, and middleware to abstract the detail of differing hardware implementations. Using a switched fabric such as Serial RapidIO is a key element, and vendors are now offering faster, lighter Serial RapidIO IP, prequalified over temperature, targeted to the needs of military DSP architectures.
System-on-Chip
The capacity, performance, and highly optimized DSP algorithms of the latest FPGA generations make them better able to support an open standards-based SoC infrastructure. Some of these available standards are AMBA, Wishbone, and OpenFPGA. All have the common objectives of offering a comprehensive set of device-agnostic architectural features and facilities to create a framework that supports the development of customers' application IP. Much of the IP support offered by COTS vendors today will be of value in the development of tested and qualified SoC ports for their future hardware products.
I/O flexibility
Typical off-the-shelf embedded systems, in form factors such as CompactPCI, VMEbus, or newer VPX (VITA 46), offer FPGA-based solutions in a variety of basecard and mezzanine formats. The recently introduced FMC (VITA 57) mezzanine standard adds flexibility by providing a small, optimally sized module for high-speed signal capture with multi-GHz serial signaling to baseboard-mounted FPGAs. This small form factor makes an FPGA and FMC mezzanine ideal partners for specialized I/O tasks such as protocol or media conversion, legacy communications, and digital video processing.
Many military sensors must operate over extreme temperatures. Because of the high power dissipation and GHz+ signaling of a typical large FPGA (10 W to 18 W), thermal design of hardware becomes critical because temperature sensitivity becomes very difficult to identify and diagnose later. Qualified and characterized off-the-shelf modules and tailored IP mitigate these risks and can significantly reduce a project's overall development time. One such qualified module is the FPE320 from Curtiss-Wright Controls Embedded Computing (CWCEC). Shown in Figure 1, it supports both the largest Xilinx Virtex-5 FPGA device types and offers the I/O flexibility of an FMC mezzanine site in the 3U VPX air- or conduction-cooled form factor.
Figure 1: The FPE320 supports both the largest Xilinx Virtex-5 FPGA device types and offers the I/O flexibility of an FMC mezzanine site in the 3U VPX air- or conduction-cooled form factor.
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The promise of significant size, weight, power, and recurring cost reductions continues to stretch developers' resources to achieve their initial development cost and time targets. Considerable gains are possible by using COTS vendor-supplied hardware modules, IP cores, libraries, and drivers. Consequently, this has been proven an effective strategy by many contractors.
To learn more, e-mail John at john.wemekamp@curtisswright.com.
