New solutions to radiation-hardened mixed-signal integration

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June 15, 2021

As of October 2020, there were nearly 6,000 satellites orbiting the earth. About 40% of those were operational. The rest are “space trash.” In March 2021 SpaceX had launched 1,300 Starlink satellites with plans to have 42,000 operational in the next few decades.

Satellite market expansion and new defense/aerospace technology are driving the need for analog/mixed signal (A/MS) radiation-hardened (RH) integrated circuits (ICs). RH field-programmable gate arrays (FPGAs) and microprocessors satisfy digital requirements, but analog parts must use either commercial off-the-shelf (COTS) ICs or develop custom solutions (for example, an RH A/MS custom ASIC). RH A/MS application-specific integrated circuits (ASICs) offer the best solution for size, weight, and power (SWaP) reduction, but are costly to develop, take a long time to design and qualify, and carry significant risk. COTS ICs do not have the development cost and qualification issues, but they are unable to achieve the same level of SWaP reduction. In addition, COTS ICs are subject to obsolescence concerns. Figure 1 summarizes the issues confronting system designers trying to achieve higher levels of integration.

[Figure 1 | Issues in achieving higher levels of integration in analog/mixed-signal ICs.]

Using analog/mixed-signal ASICs

Moore’s Law has been driving the semiconductor industry for decades. Micro­processors and FPGAs keep packing more and more transistors into smaller and smaller areas. However, analog ICs have not been shrinking at the same rate as their digital counterparts. Most analog circuits are still fabricated on process technology far behind the state of the art and fabricated on semiconductor processes with a minimum feature size greater than 0.18 micron. A simple mixed-signal circuit such as a switched capacitor filter, with fewer than 100 transistors, can consume as much area as an 8-bit microcontroller.

Digital circuits deal with ones and zeros. Consequently, adding structure to digital design has been relatively straightforward. From yesterday’s Karnaugh Maps – a graphical method of reducing a digital circuit to its minimum number of gates – to present-day hardware description languages (e.g., Verilog and VHDL) the focus has been structure. The electronic design automation (EDA) industry has helped by developing sophisticated tools enabling digital designers to work at a higher level of abstraction and make use of structured top-down design methodologies. In contrast, analog IC designers must deal with an infinite number of signal levels between one and zero. Structure has been attempted in the form of analog HDLs, but for the most part, analog designers still work at the most primitive levels, creating transistor-level schematics, running simulations, and performing manual layout. Frequently, A/MS ICs are not production-worthy after initial fabrication, which means a design change and another fabrication iteration. In fact, iterations of RH ICs can be prohibitively expensive.

Alternatives to full-custom A/MS ASICs

There are two alternatives to the traditional full-custom approach for A/MS integration: field-programmable and mask-­programmable. These alternatives are semi­custom, not full custom, yet they come with many of the benefits of full custom while minimizing the issues with development cost, design time, qualification, and risk.

The field-programmable analog array (FPAA) is the analog equivalent to the digital FPGA. Due to the nature of analog design, FPAAs have not proven to be a practical solution for implementing a wide variety of analog circuits. They are good for prototyping specific circuits, and in some cases are a good fit for production. Their biggest advantage: They can be reprogrammed in the field; be aware, however, that field-programmable parts come with increased power consumption and greater circuit area as compared with their non-programmable counterparts.

The Infineon programmable system-on-chip (PSoC) is a field-programmable alternative offering an A/MS solution integrating configurable analog and digital macro blocks around a microcontroller and memory. The analog system in a PSoC can be programmed to implement comparators, analog muxes, analog-to-digital converters (ADCs) and more. As such, the PSoC is an excellent mixed-signal solution for applications where extensive analog customization is not required.

In general, field-programmable architectures provide a good solution to size and weight, but frequently run into challenges minimizing power consumption. This situation is due to the inherent overhead associated with field programmability.

Mask-configurable arrays have been around for decades. Initially referred to as gate arrays, and later as structured arrays, these have been used extensively to achieve higher levels of integration in digital circuits. Moreover, there have been some recent advances incorporating analog circuits into structured arrays.

Specifically, A/MS structured arrays have been used to implement a wide variety of high-performance analog functions while requiring only a single metal-layer modification for configuration. Figure 2(a) shows a simple analog signal path consisting of a transimpedance amplifier (TIA), a lowpass filter, a gain block, and an ADC. Figure 2(b) shows a more complex circuit with four digital-to-analog-converters (DACs), four lowpass filters, and four gain blocks, all controlled by a serial peripheral interface (SPI). Both circuits can be instantiated on the same A/MS structured array. In other words, these arrays are capable of “sweeping up” several off-the-shelf components into a single IC – resulting in SWaP optimization. Furthermore, since a single A/MS array can be used to implement several different devices, they are essentially immune to obsolescence.

[Figure 2 | (a) simple circuit on A/MS array and (b) complex circuit on A/MS array.]

Radiation-hardening of ICs

Silicon based ICs in outer space are subject to the transient and long-term effects of radiation. Some of the common transient effects or single-event effects (SEE) include single-event upsets (SEU), single-event transients (SET), and single-event latch-up (SEL). Long-term effects generally result from exposure to ionizing energy or total ionizing dose (TID) and typically cause transistor threshold voltage shifts and mobility degradation.

The two most common approaches to minimizing the effects of radiation are radiation hardened by process (RHBP) and radiation hardened by design (RHBD). RHBP requires a specialized semiconductor process such as silicon-on-insulator (SOI), a process that is generally more costly and not widely available. RHBD is a series of electrical and layout techniques that when properly applied, can mitigate the effects of radiation on commercially available, bulk CMOS processes. Commercial semiconductor foundries typically manufacture several thousand bulk CMOS wafers per month and have process controls in place to ensure minimal variation from die to die, wafer to wafer, and lot to lot. TID levels greater than 300 krad(Si) and SEL greater than 80 MeV-cm2/mg (LET [linear energy transfer]) using RHBD on commercial bulk CMOS processes have been achieved.

Either RHBP or RHBD work well with A/MS array technology. Once an array has been qualified for radiation and reliability, new devices created by instantiating a new design on the qualified array do not require additional qualification (qualification by similarity). This can save substantial time in development and qualification.

James C. Kemerling is the chief technical officer at Triad Semiconductor. He is responsible for analog and mixed-signal mask-programmable technology development. His background includes over 30 years of experience with mixed-signal IC design and system-level development. He has published several papers in analog circuit design and signal processing. He can be reached at [email protected].

Triad Semiconductor   www.triadsemi.com