Software-defined radio (SDR) is not a new technology for the military, having been developed for defense communications. However, it has evolved beyond the Joint Tactical Radio System (JTRS) program, which is now obsolete. Although JTRS is no longer an active program, some variations of the system have survived, like the Rifleman Radio, MIDS J, and the HMS Manpack.

The military needs an enhanced communication system to enable collaboration, improve sharing of information, and facilitate shared situational analysis. Furthermore, the military needs a system that is able to engage in spectrum jamming and handle synchronized ground and airborne radio networks.

Software-defined radio … defined

SDR is a wireless communication device in which the transmitter and receiver modulation/demodulation occurs in software. As a result, the functionality is modified or changed by software alone, obviating the need to make any physical changes to the hardware. Further, it does not require the use of capacitors and resistors, as the software-based filtering algorithms can be utilized to select specific frequencies.

With SDR, the algorithms can be both downloaded and adapted over the life cycle of the hardware. SDR is also capable of incorporating new functionality enabling it to do much more than voice and data transmission.

As SDR technology evolved, it solved the problem of needing multiple devices to engage in military communication. As SDR is software-driven, functions like encoding/decoding and modulation/demodulation are no longer hardwired and can be modified by software. These features mean that users can adapt to changes in the environment by making changes to the software to perform tasks such as changing modulation schemes, frequencies, and migration.

SDR is also used to monitor communications on several different frequencies, including VHF, UHF, and HF. Several different protocols – such as CDMA, GSM, Bluetooth, WiFi, and LTE – can be operated at the same time while being combined with the ability to monitor a large portion of the spectrum while supporting these protocols. That being said, at the present time, military SDR is facing issues with phase coherency and latency of multiple input/multiple output (MIMO) systems.

Achieving true phase coherency

For any application requiring more than one radio chain (e.g., radar, beamforming, 3GPP (LTE), other cellular environments, MIMO applications), there is a significant challenge in ensuring that there is a known phase coherency and time delay.

Attaining true phase coherency between several channels of RF signal acquisition requires all clock signals to be shared directly between each ADC and downconverter. However, synchronization becomes increasingly easier with simple downconversion architecture. (Figure 1.)

Figure 1: Clock distribution architecture.

Systems that use single stage downconversion or direct downconversion (zero-IF) engage fewer local oscillators (LO). Most of the time, the LO signals can be shared directly between down-converters. In many cases, LO signals can be shared directly between downconverters, making phase-coherent measurements possible.

Consider the following scenario that involves the synchronization of four receive chains set up as a direct conversion quadrature receiver. The LO can be derived from an on-board oven-controlled crystal oscillator (OCXO), or it can be accepted from an external source. In the case of the latter, a common LO can also be shared between two or more separate units. Further, the OCXO can supply a common reference output for the use in some applications.

The OCXO provides a very stable (± 5ppb) signal that can be tuned using a nanoDAC. The source is then buffered to provide two outputs (one for an external reference clock and one as the primary output for the system internally) where the primary output goes to an ultra-low-noise clock divider and delay, which enables phase shift/group delay capabilities. After the divider, the output goes to the first low-jitter clock generator in the system.

The clock conditioner, by default, has a 10MHz input and uses the internal Phase Locked Loop (PLL1) to control a 100 MHz low phase-noise VCXO. This locks the ultra-low phase-noise 100MHz VCXO to the stability provided by the 10MHz input. The 100 MHz VCXO output subsequently drives PLL2 of the first clock conditioner. This provides a 322 MHz JESD204B (subclass 1) device clock and sysref clock to the converters and transceivers (ADC, DAC, and FPGA).

A buffered copy of the 100 MHZ VCXO output is also provided to a second clock conditioner, through a second clock divider. The buffered output drives the second PLL of the second divider and provides clocking to all frequency synthesizers for each front-end channel. (Figures 2 and 3.)

As a result, this default configuration allows for a known (in-phase) deterministic relationship for all outputs.

Figure 2: and Figure 3: Transmit radio architecture (top) and receive radio architecture (bottom) demonstrating high-frequency and baseband stages.

Visualize phase-coherent measurements in the time domain

All it takes is a limited knowledge of DSP techniques and phase-coherent downconversion, which can be used to investigate sophisticated methods of calibrating a phase-coherent measurement system.

This can be achieved by using a vector signal generator connected to the system and a power splitter. As all RF front ends will be tuned to the same center frequency, the measurement system can be calibrated easily by analyzing each of the analyzer’s down-converted baseband waveforms.

Baseband sampling, both I and Q, enables direct access to the phase data of an acquired waveform containing both phase and magnitude data. Various software platforms can be used to coordinate the domain and calculate the phase information of each sample. This is done by computing the arctangent of Q/I.

Two important tasks can be accomplished by observing the phase data from an IQ waveform: First, fine adjustments can be made to the start phase of each NCO by measuring the phase information, which then compensates the variation in cable length for both analyzers. The calibration needs to be performed only once to remove the residual skew.

The Crimson TNG SDR platform from Per Vices has architected the clock distribution to provide a multichannel transceiver able to deliver deterministic phase coherency and latency. Its four independent receive chains and four independent transmit chains are each capable of up to 322 MHz of RF bandwidth up to 6 GHz. (Figure 4.)

Figure 4: The Crimson TNG SDR, in a 1U form factor, is powered by an Altera Arria V FPGA (5ASTMD3E3F31I3N) with an on-chip dual-core ARM Cortex-A9 processor with web-based interface.

As a result, when it comes to military SDR, multichannel phase-coherent RF measurements don’t have to be an issue anymore as today’s modular instrumentation has evolved to meet the new measurement requirements of military communications systems.

Stephanie Chiao is the Product Marketing Manager at Per Vices Corporation, where she is responsible for marketing strategy, technical promotion, and media relations. She brings over nine years of consumer and enterprise marketing experience and has worked with brands including Microsoft, Rogers Wireless, and Torstar Corporation. She holds an Honours Bachelor of Business Administration degree from the Schulich School of Business in Toronto. She may be reached at [email protected].

Per Vices www.pervices.com