Implementing analog functions in rugged and rad-hard FPGAs

Story

June 01, 2012

All-digital chips such as FPGAs have traditionally not been able to house analog blocks like ADCs, clocking functions, or power converters. Now, aerospace engineers are pulling some of these analog functions onboard FPGAs to take advantage of rugged and radiation-hardened properties.

FPGAs are transforming systems engineering for high-reliability applications. FPGAs changed the cost/reliability paradigm for embedded systems in high-reliability applications with advances in hardness and power reduction. Still challenges exist. On many embedded applications for high-reliability systems, a number of peripheral analog components such as ADCs and DACs are relied on to talk to the real world. Other system components such as PLLs and DC-DC converters are usually required to complete a system design. These peripherals impact overall cost, size, and reliability. Peripheral analog parts can also be challenging to work with and to source for radiation environments, as an example. However, to further leverage the power of FPGAs, mil/aero engineers are actively looking for ways to integrate many of these analog functions onto the FPGA. Synthesizable, digital IP cores to replace some analog functions now exist, which allow ADC, DAC, DC-DC controller, and clock multiplier functions to be implemented in fully digital processes such as FPGAs. This new ability leverages the advantages of FPGAs and helps mitigate many challenges of using analog components in high-reliability applications.

Overcoming high-reliability design challenges

Challenges to engineering for military or high-reliability applications such as aerospace are numerous. Power and weight are usually under strict budgets because they can affect operating costs and insertion costs exponentially. Physical shock, force survival, and SEU and latchup protection often mean that parts are larger, heavier, and more power hungry than commercial parts. For instance, a commercial 12-bit, 10 MHz bandwidth ADC is approx .71" by .42" and consumes 280 mW power. The equivalent radiation-hard part is .81" by .72" and consumes 335 mW power. That’s almost double the size and 20 percent more power.

Wide temperature range is another issue. Typically, temperatures of -40 °C to +80 °C are expected for many military embedded applications here on Earth. Temperature takes on another complexion in space. In satellite electronics design, for instance, normal operating junction temperature might be -55 °C to +125 °C. Monitoring this onboard temperature is key to effective system maintenance, but adding a radiation-hard ADC part to provide this function can add up to one square inch of board and require additional components and testing.

When a high-reliability design relies on peripherals such as ADCs, DACs, DC-DC converters, or PLLs, each one of those components represents a possible point of failure. Each must be qualified and tested, and each is most likely not optimally designed for the specific need. There is also always a risk that the manufacturer discontinues the part, forcing requalification of the entire system.

These challenges to working with analog components in high-reliability environments can now be mitigated by using the FPGA. This new paradigm is explored next.

Pulling analog functions onto the FPGA

Regardless of how “analog” and “digital” are defined, significant differences and integration issues exist between the two. Because of these issues, it can be very advantageous to have digital designers pull analog functions onto an FPGA and test them. Herein, “digital” is defined as using standard digital library cells and passive components for a fully synthesizable and digitally testable design. Digital IP blocks of ADCs, DACs, DC-DC converter controllers, and clock multipliers can be created in RTL format and implemented in all digital processes.

With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customized analog functions within the FPGA. Not only does this take advantage of the inherent protection properties of the FPGA, but these blocks are also a great way to utilize unused FPGA resources. Xilinx and Microsemi recognize this advantage and now partner with companies like Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analog integration problems.

Digital ADC cores yield benefits

Figure 1 depicts an example block diagram of the Digital ADC IP core. With the digital approach, Digital ADC IP cores require only a few external passive components. IP core is instantiated right in the FPGA and is much easier to implement through digital synthesis. On a Xilinx Virtex-5QV, a scenario such as that pictured in Figure 1 utilizes less than 1 percent of FPGA resources.

Proprietary signal processing enables analog sigma-delta ADC performance to be replicated with all digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some benefits are:

50 percent lower power than analog ADC parts
68 percent smaller area than analog ADC parts
Process technology independence
Reduced risk and cycle time
Digital integration, synthesis, and testing
Easier radiation-hardened design

Figure 1: An example of an all Digital ADC IP core interface

(Click graphic to zoom by 1.9x)

Performance + applications

Current performance is up to 14 bits of resolution and 100 KHz bandwidth. Bandwidth depends on the selected resolution. Current performance is suitable for a host of applications including:

Sensors – temperature, pressure, voltage, current, and acceleration
Touch-screen integration
Voice and high-quality voice
Motor control

As an example, many design teams use the radiation-hardened, 12-bit, 10 MHz bandwidth ADC part mentioned in the Design Challenges section for monitoring onboard temperature and voltage. Some FPGAs, such as the Xilinx Virtex-5QV Space Grade FPGA even have embedded diodes highlighting the importance of the temperature-sensing function. However, normal bandwidths for these types of measurements are 0.5 Hz to 10 Hz, so using bandwidth in the MHz is like driving the head of a pin with a sledgehammer. A Digital ADC IP core on a radiation-hardened FPGA can get down to 0.5 Hz bandwidth per channel and consume less than 6 mW power versus 335 mW power for the external part. Why waste critical board space and power for such a low-level task?

DC-DC power management control onboard FPGAs

Power management is becoming a larger part of overall system design. Sometimes a single design can include more than 30 power supplies. External radiation-hardened DC-DC converters retain the same difficulties as external ADCs, as described earlier. Thus, the use of these parts to control power complexity in high-reliability applications does not scale well. All-digital DC-DC controller IP now exists to take advantage of radiation-hardened FPGAs’ processes and to allow for simplification of control, redundant power supplies, infinite sequencing, and infinite throttling. An external power transistor is needed, but this can be much easier to work with than a full DC-DC converter part.

Digital clocking solutions

PLLs are some of the most widely used analog blocks for clock generation; thus, most FPGAs have incorporated PLL capability within the package. However, some FPGAs including some radiation-hardened FPGA families do not include PLLs at all. Other radiation-hardened FPGAs generally do not include the PLLs in the radiation-hardened portion of the package.

Digital clock multiplier IP can be used on these FPGAs and can provide the ability to generate any clock up to about 2 GHz with no lock time. Models show 50 ps peak and 35 ps RMS and 5 to 1 ns rise/fall. As with Digital ADC IP, very few off-the-shelf passive components are required.

Putting it together

Historically, FPGAs did not lend advantages to analog functions, forcing high-reliability design teams to use nonoptimal external analog parts. This is no longer the case, as mil/aero engineers now have robust options for integrating analog functions into any digital fabric, including radiation-hardened FPGAs. By using digital implementations of analog functions from Stellamar, engineers can add critical functionality like thermal monitoring, redundant power supplies, and clocking functions – all without adding weight, power, or size to the design. The digital synthesis and test methodology ensure the operability and greatly increase reliability. Further, these technologies can be leveraged across projects and the whole organization easily. With budgets being slashed and performance more important than ever, these digital IPs give mil/aero engineering teams the flexibility and productivity needed to meet critical mission objectives.

Allan Chin is CEO at Stellamar. He has more than 30 years of design experience with high-performance digital and mixed signal systems at various institutions such as Motorola/Freescale, Mentor Graphics, and Honeywell Military and Space. Allan can be reached at [email protected].

Luciano Zoso is CTO at Stellamar. He has more than 30 years of design experience with high-performance digital and mixed signal systems at various institutions such as Motorola/Freescale, CSELT, and Hayes Microcomputer. Luciano can be reached at [email protected].

Stellamar 480-664-9594 www.stellamar.com