Power.org celebrates 20 years of advancing Power Architecture technology

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June 20, 2011

In the 6 years since Power.org was founded, it has achieved notable success in driving collaborative innovation, helping the Power Architecture receive a nod as 2010's No. 1 worldwide market share leader in 32-bit MPUs and No. 2 worldwide market share leader in 64-bit CPUs. Key to these achievements are Power Architecture's diverse range of next-gen technologies, in addition to its burgeoning road map and ecosystem. The organization believes these factors will ensure market strength in 2011 and beyond.

Power.org, the organization that promotes and develops standards for Power Architecture technology, cited 2010 as a year of continued global growth and adoption for Power Architecture technologies in the automotive, compute, consumer, high-performance computing, industrial, medical, military and aerospace, wired communications, and wireless communications markets.

According to IMS Research’s 2010 “The Comprehensive Processors World Report,” Power Architecture products represent $4.4 billion of the total 32/64-bit microprocessor market and ranked as No. 1 worldwide market share leader in 32-bit MPUs and No. 2 worldwide market share leader in 64-bit CPUs. Power.org reports that since 1991, more than 1 billion Power Architecture technology-based chips have been built into electronics equipment such as enterprise switching and routing, base station equipment, game consoles, printers and images, network storage, access points, cars, industrial automation, servers, high-performance computers, and more. This represents remarkable growth since Power.org’s formation in 2005 and since Power Architecture technology was introduced 20 years ago.

Initially, Power.org focused on merging the three-volume PowerPC Architecture Book – which defined the instructions and registers used by application programs, the storage models, privileged facilities, and related instructions for the IBM POWER5 processor family – into the Power Instruction Set Architecture (ISA) series. This series addresses both the server and embedded spaces for 32-bit and 64-bit architectures. Power ISA 2.03, 2.04, 2.05, and 2.06 were published from 2005 to 2009, to advance and support multicore, virtualization, hypervisor technology, and power management. Power ISA Version 2.06 Revision B, introduced in 2010, allows multiple operating systems to run over multiple embedded cores, providing the requisite isolation and protection while increasing performance through full hardware virtualization. This full virtualization (aka virtual CPU) does not require any modification in a guest OS.

In addition to the evolution of Power ISA technology, Power.org – with the collaboration of its member companies – has developed a series of technical specifications aimed at lowering costs and speeding software development. These specifications include Power Architecture Platform Requirements for Embedded and Server (ePAPR, sPAPR), Common Debug Interface API specification, and the Physical Connection for High-speed Serial Trace specification aimed at improving efficiency and simplifying the debug process. In 2010, the organization released sPAPR v2.4, which improves the operation of previous versions and adds new functionality such as the Cooperative Memory Over-commitment (CMO), I/O Super Page, and Virtual Processor Home Node (VPHN) options.

Diverse range of next-gen technology

The collaborative nature of Power.org and the ongoing delivery on a silicon road map by the organization’s members have enabled Power Architecture technology to address next-generation, high-performance systems requirements across diverse applications such as networking, game consoles, and some of the most energy-efficient supercomputers in the world. Market highlights include the following:

• Automotive – More than 50 percent of all new car models, such as Ford and BMW, contain Power Architecture-based controllers in drive trains, telematics, and safety systems.
• Compute – Power Architecture is used in some of the fastest (5 GHz) and most resilient enterprise servers – including the Power Servers 4, 5, 6, and 7. “IBM WebSphere middleware on POWER7 hardware can get the lowest cost for performance in the industry – one-third that of the nearest competitor,” according to IBM (see www-03.ibm.com/press/us/en/pressrelease/33964.wss). IBM’s “Watson” computing system based on POWER7 was used to challenge all-time greatest “Jeopardy” champions.
• Consumer – Power Architecture technology is the core of the newest generation of innovative game consoles (Xbox 360, Wii, and PS3). In 2010, members drove the first Android OS port, which is now available as open source code for the embedded community.
• High-performance computing – Two of the top 10 and five of the top 20 of the world’s most powerful supercomputers are Power Architecture based (www.top500.org). IBM Blue Gene/Q, the “Greenest Supercomputer in the World,” and 13 of 25 power-efficient systems at 1,684 MFLOPS/watt are also Power Architecture based (www.green500.org).
• Military and aerospace – Power Architecture technology is the only architecture to be used in every space mission to Mars including the Spirit and Opportunity Mars rovers, the Mars Pathfinder lander, the Mars Polar Lander, the STEREO spacecraft, the IMAGE/Explorer 78 MIDEX spacecraft, and the Phoenix Mars Polar Lander.
• Wired communications – The Power Architecture serves as core embedded technology and intelligence for 50 percent of enterprise/core communications networks for switching and routing equipment among companies such as Huawei, NEC, and H3C.
• Wireless communications – Power Architecture technology is the de facto standard in the embedded telecom-in-wireless infrastructure market, suited to high-performance, low-power SoCs (multicore processing, virtualization, and energy management) with companies such as Alcatel-Lucent and Datang.

Burgeoning road map, products, and ecosystem

As Power Architecture technology enters its third decade, it will be driven by the Power Architecture silicon road map introduced in 2010. This road map includes major silicon commitments from the members of Power.org including IBM, Freescale, Applied Micro, and LSI Corporation, as well as companies licensing Power Architecture core technologies. The Power Architecture silicon road map extends the architecture’s focus on scalability, reliability, and flexibility. In addition, the road map presages performance gains because of an emphasis on multicore and accelerators as well as power management and hardware virtualization, enabling multiple operating systems to operate over multiple cores in both 32-bit and 64-bit architectures.

According to Fawzi Behmann, Director of Marketing and Strategic Advisor for Power.org, “Power Architecture ecosystem members have delivered a clear message: They are committed to ensuring the availability of the products needed to build systems leveraging the Power Architecture standard.”

Power.org members delivered on the Power Architecture silicon road map (Figure 1) with product announcements from Applied Micro, IBM, Freescale, and LSI Corporation; alliances among Freescale, Enea, Green Hills Software, and Mentor Graphics; and awards including the U.S. National Medal of Technology and Innovation, bestowed upon on the Power Architecture-based IBM Blue Gene family of supercomputers (www-03.ibm.com/press/us/en/presskit/28422.wss).

 

Figure 1: Power.org members delivered on the Power Architecture silicon road map, with several product announcements and member alliances.

(Click graphic to zoom by 1.9x)

 

2011 and beyond

In 2011, Power.org plans to approve and release the Application Binary Interface (ABI) document, which describes the low-level interface between applications and the system. The Power ABI should include information that is in both the embedded ELF ABI and the Linux ABI. It will be licensed under the GNU. In addition to full virtualization introduced in 2010 through the Power ISA 2.06 Rev. B, the organization’s technical committee is planning to introduce a Hypervisor API (h-call interface) as part of the ePAPR specification. This is intended to allow the guest and the hypervisor to communicate in a standardized way.