High-speed VPX backplane design practicesStory
July 26, 2023
Precision-engineered VPX backplanes designed to the toughest performance standards are essential for the high-speed signal demands prevalent in today’s defense applications. Backplanes are indeed the communication backbones in embedded systems and must be designed to stringent signal integrity standards to ensure timely and accurate data transmission from module to module within a system. For payloads aligned to VPX and SOSA [Sensor Open Systems Architecture] standards, high signal integrity is critical to enable fail-safe operation as systems move to higher serial bit rates supporting 100G-baseKR4 Ethernet, PCIe Gen 4 protocols, and beyond.
Meeting the performance expectations in high-speed backplane design requires practical know-how and deep design experience by teams using the latest connector technology and materials. The most up-to-date design, simulation, and test tools are necessary for validation and verification to measure the results.
The data freeway starts with the backplane
Starting with a firm foundation is essential to backplane performance. Nearly all VPX backplane PCBs are currently manufactured from FR4 materials. FR4 has a record of solid performance over decades and is noted for exceptional thermal tolerance (+180 °C) and a consistent dielectric constant (Dk). Its low coefficient of thermal expansion (CTE) at extreme temperature ranges can be critical given harsh defense environments, not to mention the physical length of backplanes in high-board-count systems. FR4 has its limits, however, when it comes to one key factor in VPX systems and it’s a big one – data rates.
FR4 is the way to go at 8 to 10 Gbits/sec. At 10 Gb per lane, that does the job for 40 GbE (40GBASE-KR4) and PCI Express (PCIe) Gen-3 protocols with signal integrity sufficient to the task. However: Higher-speed EW/RF [electronic warfare/radio frequency] applications in every form now require data rates and network connectivity that surpass those levels. Chip manufacturers continue to respond quickly to market needs and as a result, new Sensor Open Systems Architecture (SOSA) aligned 3U and 6U payload modules now must support 100 GbE (100GBASE-KR4) and PCI Express (PCIe) Gen-4 protocols in processing, FPGA [field-programmable gate array], and switching products. With these advancements, the associated per lane upshift in data rate requirements goes from 10 Gbits/sec to 25 Gbits/sec, well beyond FR4 capabilities in terms of signal integrity.
Enter high-speed laminates
Faster protocols now being rolled into silicon need faster backplanes – you can’t have a superhighway feeding into a dirt road. While that analogy may be extreme, the fact is that backplane data-rate capability needs to keep pace in order to avoid bottlenecks. Tachyon 100G from Isola is an example of a high-speed laminate that enables scaling current VPX modules and protocols to higher-speed systems through board and backplane designs. Its low loss performance and ultra-smooth copper support high-data-rate applications at 100 GB/sec and beyond. It enables greater stability over a wider frequency and temperature range versus FR4, two very important performance features given the higher speed and hotter system payloads coming into play for VPX systems.
The fiber/resin composite makeup of any PCB is key in ensuring a consistent dielectric constant. Fiber/resin composite PCB materials are inhomogeneous and anisotropic (not uniform/have a grain) and so propagation speed can vary depending on the location of traces. In typical FR4 materials (Figure 1), signals running over traces that cross a fiber-rich area (#1) encounter a different dielectric constant as they traverse the board as opposed to signals traversing combined resin/fiber areas (#2). This can lead to timing skew and signaling errors due to differing propagation speeds from one trace to the other.
[Figure 1/1a ǀ Typical FR4 materials compared with high-speed materials.]
High-speed laminate, by comparison (Figure 1a), features a mechanically spread glass makeup and is more electrically uniform compared with FR4. Filaments are spread mechanically in a high-density weave resulting in the elimination of resin gaps and therefore more electrical uniformity. The homogeneity of the material means consistent signal performance regardless of where the trace traverses the board. This consistency helps to ensure similar propagation speeds and dielectric constants and can reduce signal-timing issues.
The exit and entrance ramps – VPX connectors
From silicon to module to connector and beyond, all was well prior to about 2018 when PCIe Gen3 and 40 GbE were the predominant/most-used high end of the data-transmission protocols. Connectors defined by VITA 46 served well for years at the prevailing speeds. As advanced EW/RF applications came along, however, with their inherent increased data rates, PCIe Gen4 and 100 GbE started to find broader application and the limits are being breached. In parallel with board advancements, VPX connector manufacturers introduced long-awaited design improvements that ensured those high-speed signals could make it off the VPX module and across the backplane from slot to slot and slot to I/O with the signal integrity necessary for the application.
In January 2021 the ANSI/VITA 46.30-2020 Higher Data Rate VPX Standard was introduced to address high-speed connector design for 100GbE and PCIe Gen 4 protocols. VITA 46.3, as it’s commonly known, paved the way for 25 Gbaud speeds per wafer, or lane in VPX terms. One lane is also known as an ultrathin pipe; link aggregation in turn converts four lanes into one fat pipe supporting 100 Gbaud and 64 Gbaud per fat pipe link that then achieves the necessary data rates for 100 GbE and PCIe Gen 4, respectively. The R-VPX EV02 from Amphenol and the RT3 connector from TE Connectivity meet the ANSI/VITA 46.30 and are now seeing more use in newer applications running 100 GbE and PCIe Gen 4 protocols. (Figure 2.)
[Figure 2 ǀ Pictured: R-VPX EV02 high-speed connectors from Amphenol]
An important difference between the original VITA 46.0 connector and the new higher-data-rate connectors as defined in ANSI/VITA 46.30 is the pin size at board termination. Pins are reduced in size so that crosstalk is minimal and impedance discontinuity is reduced at the connector/PCB junction. For the high-speed signals, VITA 46.30 standard points to solder tails instead of smaller compliant pins. Solder tails are terminated in microvias in the PCB to improve signal integrity. The good news is that connectors compliant to VITA 46.30 are backwards-compatible to legacy VITA 46.0 connectors and follow the same form factor. This fact means that 100 Gb-capable VPX modules may be plugged into lower-speed 40 Gb-capable backplanes and vice versa.
Manufacturing: controls are key
Experienced high-speed backplane suppliers know that the production controls for high-speed backplanes are just as important as the upfront engineering efforts. Adherence to baseline design principles for successful backplane realization is critical; moreover, the assembly of high-speed backplanes relies on controlled and well-understood manufacturing processes to ensure that the engineering and design work investment is not diminished during the production of the backplane.
One area of importance is conductor surfaces. Conductors on PCBs do not have perfectly smooth surfaces, but rough copper improves peel strength of laminate. On the other hand, conductor surface smoothness is key in controlling the consistency and optimization of signal speeds as they pass along the conductive copper foil. Tachyon 100G uses very smooth copper foil -- VLP-2 (2-micron) for improved performance.
When the copper surface is rough, the effective conductor length extends as current follows along the contours of the surface along the topography of the copper surface. At high frequencies, the effective resistance of the copper increases relative to the additional distance over which the current travels. Manufacturing methods must balance the need for copper/laminate adhesion with the need for smooth surfaces for consistent signal speeds.
Regarding PCB thickness, maximum thickness is dictated by the minimum connector through-hole diameter. The ratio of board thickness to hole size generally cannot exceed 10:1. High-speed connectors that can handle 25 Gbaud use nano tail pins as mentioned earlier that require smaller holes (0.014 inch) versus standard VPX connectors (0.022 inch). This means that as signal speeds increase and high-speed connectors are introduced in the assembly, through-hole diameters must decrease as does maximum board thickness and hence maximum layer count. This board-thickness limitation forces circuit designers to use board layouts that minimize layer counts yet maximize signal efficiency. (Figure 3.)
[Figure 3 ǀ Backplanes from LCR Embedded Systems use advanced design methods to facilitate high-speed systems aimed at defense applications.]
Validation – measuring the bumps in the road
Testing backplanes for performance at 25 Gbaud requires increased scrutiny as opposed to testing at 10 Gbaud.
Circuit designers understand that s-parameters represent the dynamic response of electronic components and circuits to high-speed signals. Channel parameters are an interpretation of the s-parameter data that can be used to evaluate overall channel performance. In VPX backplanes, channel parameters are used to evaluate signal integrity as signals move between VPX modules – the VPX channel in this case. S-parameters from each channel component are combined to yield overall performance (channel compliance) for insertion loss, return loss, crosstalk, and so on.
For backplane performance at or below 10 Gbaud, ANSI/VITA 68.1-2017 defines a budget-margin criterion for signal integrity that establishes channel compliance. This guideline enables developers to design VITA 68.1-compliant backplanes that support required bit-error rates (BER) for multiple fabric types when the backplane includes components that are also compliant to VITA 68.1 budget criteria. For higher rates with reduced compliance margins, the entire channel must be closely considered, and so the smaller margins cannot be pre-allocated. Validation must therefore involve full-channel COM (channel operating margin per IEEE 802.3 Ethernet) and statistical eye diagram analysis for PCIe.
That’s where VITA 68.3 comes in: For speeds in excess of 10 Gb/sec VITA 68.3 will use simulations to establish a set of corner-case reference s-parameter models for VPX modules and backplanes. This setup enables simulation of the entire channel without detailed knowledge of exactly what module or what backplane combinations will eventually be connected. Any given design will then need to demonstrate compliance through simulation when inserted into a defined set of end-to-end channels using reference s-parameter models.
Confidence in any high-speed design begins with simulation. The entire end-to-end channel must be simulated even when only designing a module at one end or the backplane. Compared to direct measurement, simulation does not rely on external equipment and makes it easier to isolate components and other elements from the rest of the channel for the module or backplane. COM (for Ethernet) and PCIe reference packages are now provided with simulation software and VPX connector modules are available from the connector manufacturers. Post-simulation provides a detailed model of the design that can be shared with customers and vendors per VITA 68 requirements without revealing proprietary design features.
VPX going forward
VPX and the progression towards modular systems architecture has resulted in raised expectations regarding time to market – or, to put it in more absolute terms, time to theater – for new system deployments. There’s an insatiable demand for improved performance and reliability driven by applications requiring high-speed signal processing. Optimal backplane design that results in the highest signal integrity relies on a firm foundation based on a combination of leading-edge materials, connectors, plus test and manufacturing methods. As the VITA Standards Organization plans ahead for ever-increasing data rates, system integrators with deep design experience must be experts in every aspect of backplane design. Keeping pace will ensure current and future mission-ready solutions meet the needs of the warfighter.
David Jensen is a senior electrical design engineer at LCR Embedded Systems who has more than 25 years of electronics PCB design and embedded integration experience in the communications (telcom/datacom) and military industries.
Steve Gudknecht is the marketing and communications manager at LCR Embedded Systems. Steve has more than 20 years of experience promoting and managing solutions for the embedded computing industry. Steve also served as a product and marketing manager for Elma Electronic.
LCR Embedded Systems · https://www.lcrembeddedsystems.com/