3U VPX poised to serve small UAVS

Story

July 27, 2012

Steve Edwards

Curtiss-Wright

As the DoD takes advantage of reductions in SWaP, smaller enclosures, such as 3U VPX, are reaping the benefit. However, today's 3U VPX backplane topologies will need to be retrofitted to fully capitalize on modern processing capabilities.

Thanks to significant advances in performance and Size, Weight, and Power (SWaP) efficiency delivered by the newest generation of CPUs, General Purpose Graphics Processing Units (GPGPUs), and FPGAs, the military is increasingly turning to smaller, lower-cost Unmanned Vehicles (UVs) as platforms for compute-intensive ISR applications.

As a result, the use of 3U VPX modules in smaller UVs is also gaining traction. Until recently, 3U modules were ill suited for performance-hungry ISR applications; however, today’s latest-generation CPUs such as Intel’s third-gen Core i7, NVIDIA’s 240-core Fermi Architecture GPGPUs, and Xilinx’s Kintex-7 FPGAs have significantly improved processing performance per watt to create small, power-efficient ISR platforms. Add data storage for recording and 3U systems comprise a powerful solution for UV ISR.

Newest-generation technology supports ISR applications

As thermal management techniques have advanced, open architecture systems are now better able to optimally leverage the full potential of the latest multicore, low-power processors such as the Core i7 without having to derate performance in deference to heat dissipation. The use of ruggedized MXM modules enables the deployment of the latest, highest-performance NVIDIA GPGPUs in small form factor embedded systems. Xilinx’s new Kintex-7 family of FPGAs is especially well-suited for ISR applications, enabling the design of XMC FPGA modules that boast ~3x the performance of earlier-generation modules while keeping power dissipation almost the same.

As data storage moves from heavier, less reliable spinning-disk media to large-density, solid-state designs, small form factor system designs receive the benefit. Thanks to OpenVPX, there is an architecture that enables integrators to leverage these advanced technologies into systems and scale them. Curtiss-Wright Controls Defense Solutions’ VPX3-491 features an NVIDIA Fermi architecture GPU device on a 3U VPX board ideal for small unmanned vehicle ISR applications (Figure 1).

Figure 1: The VPX3-491 from Curtiss-Wright Controls Defense Solutions

(Click graphic to zoom by 1.9x)

Taking 3U processing to the next level

Making these compact, small form factor systems even more suitable for UVs will require new 3U VPX backplane topologies that are being proposed for the next revision of the standard. Today’s 3U topologies cannot take full advantage of the high-performance bandwidth supported by the most advanced CPUs, GPGPUs, and FPGAs.

At its inception, the designers of OpenVPX envisioned that 3U would predominately serve as a replacement for moderate-performance 3U CompactPCI or AdvancedMC cards. The ability to deploy 500 Gigaflops or more in a five-slot 3U chassis was not envisioned. But it is now becoming clear that five-slot 3U VPX systems that combine storage, GPGPU, SBC, and I/O functionality have the potential to be a disruptive force in the smaller UV market. These units will range from 10 to 20 lbs. and 50 to 250 W in a mailbox-sized platform. What is anticipated, essentially, is the shrinking of Global Hawk-level capabilities down to a UAV the size of a desk.

Embedded COTS suppliers have most of the pieces today to make this vision a reality. But what will really accelerate this technology shift is a dialogue between the sensor-engineering community and the embedded processing system community. While there is a lot of legacy I/O in the field, there has been no organized initiative to standardize the interfaces and interconnects used by leading ISR sensor vendors. Today interfaces used in ISR sensors vary from system integrator to system integrator. It is not uncommon to find one vendor using 10 GbE, while another uses 1 GbE, while yet another uses 1553 and a variety of video interfaces.

The plethora of interfaces used in the ISR sensor market has impeded the ability of COTS embedded system designers to support all of the I/O types on a single box, especially considering the SWaP-constrained nature of the technology. What might help encourage the development of standards in the sensor I/O arena would be the creation of a consortium in the OpenVPX community that reaches out to sensor providers to explore the definition of three to five common I/O types for airframe communications, uplink/downlink communications, and sensor interfaces. By defining a common suite of interfaces, system designers will get both the benefits of leading-edge COTS system designs and the cost and time-to-market benefits of COTS upgradability.

To learn more, e-mail Steve at [email protected].