SWEPT up for real?

Story

July 20, 2007

I had no idea that we would be Slashdotted when we posted the Raytheon news release entitled Raytheon Develops World's First Polymorphic Computer on our Mil-Embedded.com RSS newsfeed March 20. I thought I would try to go deeper behind the scenes for the back story on this.

I had no idea that we would be Slashdotted when we posted the Raytheon news
release entitled Raytheon Develops World’s First Polymorphic Computer on
our Mil-Embedded.com RSS newsfeed March 20. I thought I would try to go deeper
behind the scenes for the back story on this.

In 1999, Robert Graybill began his term as program manager
at DARPA, laying out a vision for embedded computing. “As we look at future systems, they
are anything but bounded and will need to evolve with each mission and with
technology advances. Translated into computer architecture terms, this means
the architecture must be able to support a broad spectrum of functionality
by morphing on demand over time. At the same time, each unique mission’s
functionality, size, weight, energy, performance, and time requirements must
still be satisfied, and hence the term polymorphous computing.”

I like the SWEPT acronym Graybill proposed better than what we usually call SWaP (Size,
Weight, and Power), as power can be a bit ambiguous. 

In May 2005, Raytheon was awarded the contract for the Morphable Networked
Micro-Architecture (MONARCH) project, working with the Information Sciences
Institute (ISI) at the University of Southern California, with assistance from
IBM, the Georgia Institute of Technology, and Mercury Computer Systems.

On March 20, we received the news of the first breathing prototypes of a MONARCH
chip delivered from the IBM fab to Raytheon. MONARCH combines six RISC cores
coupled into a Field Programmable Computing Array (FPCA), with a morphing interconnect
to optimize memory access and routing between clusters, and two RapidIO ports
for connecting industry-standard devices.

Jeff LaCoss, ISI principal architect, says: “The RISC engines are only
a part of the MONARCH chip. Stream processing (such as FFTs) are handled by
Raytheon’s Field Programmable Computing Array (FPCA). The RISC ISA is
an ISI invention developed for the DIVA Architecture, an earlier DARPA-funded
project at ISI. The ISA is modeled on the MIPS R3000 ISA, and is also much
like the Hennessey and Patterson DLX ISA.”

The RISC engines and the stream processing FPCA can work
closely together. According to LaCoss, the RISC processors have two modes
of operation: “They
can run in 32-bit mode like an R3000 with floating point. However, the chip
can morph and assign resources from the stream processor to the RISC
engines. These resources become a 256-bit WideWord data path that behaves similarly
to a SIMD processor executing in place of the RISC 32-bit data path. That is,
the RISC engine runs instructions for either 32- or 256-bit mode.”

This gives MONARCH the horsepower for complex algorithms,
and LaCoss gives an example. “A killer app for the WideWord is the corner-turn algorithm,
something that conventional CPUs are terrible at. The WideWord can turn an
8 x 8 array of 32-bit objects in around 150 clock cycles, 8 memory reads, some
permutations, and 8 memory writes. A conventional processor (such as an R3000
or Power Architecture) must do 64 reads to get the data, 64 writes to store
the data, plus a whole bunch of addressing calculations. That’s a lot
of clocks and instructions. Caches help conventional processors (MONARCH has
none) but don’t cure the memory-access latency problems.”

The RISC engines run an RTEMS-derivative RTOS written by Exogi under subcontract
to ISI. Software tools include a production-quality C++ 4.1 compiler written
for ISI by CodeSourcery. The assembler is an ISI tool based on GNU gas.
There are cycle-accurate simulators for the RISC engines, the FPCA stream-processing
fabric, and the chip as a whole.

Boutique processors developed for specific jobs should
help optimize SWEPT – Size,
Weight, Energy, Performance, and Time – to new levels.