Introducing Gen 5 VPX

Story

March 21, 2018

Ivan Straznicky

Curtiss-Wright

A new, higher-performance era of VPX (VITA 46) computing was launched in January - at the Embedded Tech Trends (ETT) 2018 Conference in Austin, Texas - with the announcement that Gen 5 VPX data rates will run on today's standard VPX connector. The initial Gen 5 VPX protocols are expected to be 100 Gigabit Ethernet (100G-KR4) and Infiniband EDR [enhanced data rate]. In addition, a next-generation VPX connector, the MULTIGIG RT3, which is able to support data rates of 25.8 Gbaud, also made its debut.

A new, higher-performance era of VPX (VITA 46) computing was launched in January – at the Embedded Tech Trends (ETT) 2018 Conference in Austin, Texas – with the announcement that Gen 5 VPX data rates will run on today’s standard VPX connector. The initial Gen 5 VPX protocols are expected to be 100 Gigabit Ethernet (100G-KR4) and Infiniband EDR [enhanced data rate]. In addition, a next-generation VPX connector, the MULTIGIG RT3, which is able to support data rates of 25.8 Gbaud, also made its debut.

The impressive performance breakthroughs follow last year’s announcement that Gen 4 VPX can support Gen 4 PCIe at 16 Gbaud using the standard MULTIGIG RT-2 connector. Last year’s surprising Gen 4 announcement resulted from the development of new advanced design rules and features to prove that the higher bandwidths are reliable for use in critical military and aerospace applications. These same design rules also proved key to the analysis and verification of Gen 5 VPX signal integrity over a standard VPX backplane.

The art of validating advanced VPX data rates, such as Gen 5’s 25-plus Gbaud signaling rates, requires a thorough understanding of the VPX transmission channel and its constituent elements. That’s because each part and interface in the VPX channel has unique electrical characteristics, each of which can degrade the transmitted signal. For example, insertion losses, return losses, and crosstalk caused by effects like impedance mismatches, parasitic inductance and capacitance, and weave skew all come into play. Copper-trace widths and lengths, via barrel lengths and stub lengths, and laminate material choices must all be carefully considered. At these high speeds, even more subtle effects must be considered and resolved, including things like weave skew mitigations and trace surface roughness. Several of these factors also have tolerances that will significantly affect results. In general, all these factors must have appropriately conservative assumptions when analyzing Gen 5 VPX signal integrity.

Once all the correctly conservative assumptions were in place to verify Gen 5 VPX data rates, and advanced design features were added, the results proved that VPX channels are able to pass signal-integrity analyses in a large number of configurations with margin. Further support for the new data rates was provided when TE’s Michael Walmsley unveiled its next-generation VPX connector, the new MULTIGIG RT3. (Figure 1.) The new connector boosts support for VPX backplane speeds from the respectable 16 Gbaud rates delivered by the MULTIGIG RT-2, to the 25.8 Gbaud level. A key requirement and feature of this new VPX connector is its backwards compatibility with the earlier MULTIGIG RT-2 connectors.

Figure 1: The MULTIGIG RT3 VPX connector enables 25.8 Gbaud rates and is backwards-compatible with earlier MULTIGIG connectors. (TE Connectivity photo.)

In the earliest days of the VPX standard, now recognized as the embedded military and aerospace market’s architecture of choice, the channel and connector system were rated at up to 6.25 Gbaud, providing plenty of headroom for the 2.5 to 3.125 G limits established by “Gen” 1 VPX. Because the next generation of VPX supported 5.0 to 6.25 Gbaud backplane rates, proving signal integrity was also relatively straightforward. When Gen 3 Serial Fabrics for VPX debuted, about five years ago, its significantly faster 8.0 to 10.3 Gbaud rate span was considered a daunting hurdle, and in fact proved to be one. In particular, the return loss and ICR (insertion loss to crosstalk ratio) parameter proved problematic for effective data transmission at the connector footprints. Nevertheless, leading commercial off-the-shelf (COTS) vendors tackled and overcame the technical challenge.

To ensure sufficient channel operating margin (COM) for VPX Gen 5, many system emulations were performed. Two of the 3U system emulations that were performed were for a 14-slot system and a 12-slot system. Both of these emulations and analyses used the standard VPX MULTIGIG RT2-R connector. Larger 6U systems were also emulated and analyzed, and acquired the additional margin required to pass the IEEE COM requirement of 3 dB by using the new MULTIGIG RT3 connector. For these tests, the basic transmission path, or channel, for VPX systems includes a transmitting chip on a TX module, a receiving chip on the RX module, and two sets of mated VPX connectors with a backplane in between.

A couple of important measures of signal integrity on this channel are the BER [bit-error rate] and the eye diagram. (Figure 2.) The eye diagram must show enough of an “opening” in order to “see” the data transmission (e.g., PCIe Gen 4 needs 15 mV of eye height peak to peak and 0.3 UI [unit interval] eye width). The BER requirement is typically a maximum of 10 to 12 bit errors per unit time, and is calculated or measured by dividing the number of bit errors by the total number of transmitted bits. The design rules applied to the Gen 5 VPX data rates passed these tests with flying colors.

Figure 2: An eye diagram measures signal integrity to ensure sufficient channel operating margin.

At ETT, in parallel with TE’s announcement, Curtiss-Wright Defense Solutions announced that it will support the Gen 5 VPX data rates (e.g., 25 Gbaud 100G Ethernet and Infiniband EDR) on its next-generation Fabric100 rugged commercial off-the-shelf (COTS) embedded modules and systems. The next step is for new interconnects such as the MULTIGIG RT 3 connectors to become extensions to VITA standards, which is expected later in 2018. The benefit for system integrators and the warfighter? Significant gains in bandwidth and functionality for tomorrow’s embedded computing systems.

Ivan Straznicky is a Curtiss-Wright Fellow.

Curtiss-Wright Defense Solutions www.curtisswrightds.com