Sensor Open Systems Architecture (SOSA) – Taking EW systems to the next levelStory
October 20, 2021
The Sensor Open Systems Architecture Technical Standard (SOSA) – which will bring many benefits to designers of radar systems – will also have a beneficial effect on the design of electronic warfare (EW) systems.
One of the main differences between radar and electronic warfare (EW) system architectures is that radar systems are primarily receivers of sensor data. While some radar systems may transmit energy to excite the targets, other radars may be completely passive. EW sense-and-response systems, on the other hand, have significantly more bidirectional activity compared to a radar system. Moreover, EW systems must respond after sensing a signal as close to instantaneous as possible. That capability means that low latency is essential to enable signals to get in and out from the system as quickly as possible.
Another attribute of EW is that system designers must constantly respond to new threats and come up with appropriate ways to respond. EW is a continuously evolving domain for which the concept of QRC [quick response capabilities] is vital to introducing new capacities rapidly and easily. These capabilities can range from those that correctly identify new threats to new techniques that nullify a threat. Techniques may involve jamming the incoming signal or distorting/delaying the natural response to confuse whatever weapons may be zeroed in on the target platform.
The SOSA Reference Architecture facilitates these objectives by providing a definition of SOSA modules, hardware elements (for example, plug-in cards), and software environments that follow SOSA Technical and Business Architectural Principles as well as Quality Attributes. These elements have well-defined, open, and exposed interfaces, and are verified conformant to those SOSA Quality Attributes.
Within the SOSA Reference Architecture, the SOSA Modules were created as logical entities that encompass behaviors and functions. SOSA Modules are instantiated in a variety of ways, with one example being the instantiation of SOSA modules for EW in software.
The use of SOSA Modules (no matter how they are instantiated), along with their associated Quality Attributes and open and exposed interfaces, help ensure that the system is able to adapt to the changing needs of spectrum warfare by making it easier to replace or upgrade modular pieces of the system. The ability to replace software or firmware to add a new capability to the EW system is critical because it means the ability to rapidly introduce new waveforms or techniques to address constantly changing threats.
At a plug-in card (PIC) level there are a few physical attributes that lend themselves nicely to EW systems. The key to any EW system is the front-end sensor processor, which is typically a tuner or FPGA [field-programmable gate array] card. It is important that the front end of the system is capable of supporting a large amount of sensor I/O and can distribute this data across a high-performance fabric to other downstream plug-in cards in the system. (Figure 1.)
[Figure 1 | Annapolis Micro Systems’ WILDSTAR 3XBP 3U OpenVPX FPGA processor is 100GbE-enabled and aligned with the SOSA Technical Standard.]
The primary “workhorse” plug-in card profile (PICP) defined by the SOSA Technical Standard for 3U-based systems is the payload PICP. This profile differs from the I/O-intensive PICP used for single-board computing (SBC) cards in that it provides backplane apertures which can be used for optical or coax cables, as well as a wide expansion plane (EP) interface which can send data for downstream processing, and a data plane (DP) fabric interface for sending data through the network fabric.
Two variants of the payload PICP [a primary (Figure 2) and secondary (Figure 3)] are shown in the figures where there is a tradeoff within the upper half of the backplane P2 connector, between more aperture space for sensor input/output versus a wider EP for downstream data processing. For EW systems, where both input and output signals are needed, the primary payload PICP in Figure 2, with wider aperture space, provides the capability for supporting a larger number of RF or optical transmit and receive signals.
[Figure 2 | ANSI/VITA 65.0 Payload Slot Profile SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n]
[Figure 3 | ANSI/VITA 65.0 Payload Slot Profile SLT3-PAY-1F1U1S1S1U1U4F1J]
Either of these PICPs support rear-panel fiber or coax interfaces, which are optimal for EW sensors. The rear-panel approach enables cabling to be handled in the sensor-processing chassis itself, eliminating the complex cable management problem that results from having a proliferation of cables at the front panel. More specifically, positioning the cables within the chassis rather than on the front panel eliminates the need to disconnect cables when replacing a PIC. This setup not only saves time but also reduces wear and tear on the connectors themselves and overall makes system integration and maintenance significantly easier. With new high-density connectors, developed by the market and standardized by VITA and The Open Group’s SOSA Consortium, the number of sensors supported is also much higher than can be supported with just the standard VPX connectors on the backplane or with the types of connectors that are typically used on the front panel.
In 6U, where more backplane pins are available, all processor profiles support one or two full connectors’ worth of apertures as well as wider DPs and EPs.
Over the last 10 or so years, it seems that until recently it was the norm to have most EW analog signals brought into an FPGA card or front-end processor card via an FMC mezzanine mounted on that card or directly to the card via connectors on the front panel. In either case, there are front-panel connections to cables, and from there, connections to the sensors themselves.
In the last few years, however, the VITA 66 and VITA 67 specifications started adding provisions for connectors on the backplane that could support optical or coax. For coax, the connectors take the analog signals from the board and connect to high density cables on the backplane. For optical signals, the connectors can interface to blind-mate cables on board or include a transceiver that translates signals on onboard copper traces on the board to optical signals on the backplane cables.
Today is seeing a mixture of analog sensors and smart sensors with optical backhauls being deployed; both types are critical and in many cases may be mixed in the same system.
The analog or optical interface is another area that can benefit from standardization. With a proliferation of cable connector types, densities, and pin assignments used on different front-end cards, having a common set of configurations makes it easier to support and easier to substitute in a different PIC. The challenge remains, however: how to do this in a way that also provides the flexibility to handle the wide range of antennae and sensor front ends that exist?
Supporting the higher-density connectors as well as prioritizing the order of pin assignments and providing a few options helps that problem significantly. The SOSA Technical Standard defines connections not only at the PIC level but also at the chassis level. The SOSA Reference Architecture is intended to support EW sensors plus radar, EO/IR [electro-optical/infrared], SIGINT [signals intelligence], and communications sensors as well.
The SOSA Technical Standard also includes the definition of signals and signal characteristics as well as the means by which different information is communicated to different entities. A major portion of this capability has been adopted from the Modular Open RF Architecture (MORA), which itself is an extension of the VICTORY [Vehicular Integration for C4ISR/EW Interoperability] architecture, which was developed to ease the integration of RF systems in ground vehicles. MORA is important to EW systems in that it adds low-latency transport capability and streaming functions which are critical to time-sensitive applications. (Figure 4.)
[Figure 4 | The Curtiss-Wright CMOSS Starter Kit 3U OpenVPX system integrates a VPX3-687 VICTORY network switch module, VPX3-673 A-PNT card, and VPX3-1260 SBC in a SOSA Technical Standard 1.0 aligned chassis.]
Putting all this together, the SOSA Technical Standard provides a solid framework for supporting interchangeable entities, which are key to the interoperability, modularity, portability, and upgradeability principles, all of which are what the SOSA Reference Architecture is all about.
Denis Smetana is a senior product manager for FPGA and DSP products for Curtiss-Wright Defense Solutions, based out of Ashburn, Virginia. He has more than 30 years of experience with ASIC and FPGA product development and management in both the telecom and defense industry and over 15 years of experience with COTS ISR products. He has a BSEE in electrical engineering from Virginia Tech.
Curtiss-Wright Defense Solutions https://www.curtisswrightds.com/